Figure 2-6 General Line Card Data Plane Block Diagram - Cisco ASR 9000 series Reference Manual

Ethernet Line Cards
Figure 2-6
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The 40x1GE line card, 8x10GE line card, and 4x10GE line card have four NPUs per card. There are two
data paths from the NPUs. The primary path is to a bridge FPGA, which manipulates the header and does
interface conversion, then to the fabric interface ASIC where packets are where packets are queued using
VOQ and then sent to the backplane where they flow to the RSP fabric. This path handles all main data
and also control data that are routed to the RSP card CPU. The second path is to the local CPU through
a switched Gigabit Ethernet link. This second link is used to process control data routed to the line card
CPU or packets sent to the RSP card through the fabric link.
The backplane Gigabit Ethernet links, one to each RSP card, are used primarily for control plane
functions such as application image download, system configuration data from the IOS XR software,
statistics gathering, and line card power-up and reset control.
A CAN bus controller (CBC) supervises power supply operation and power-on reset functions. The CBC
local 3.3V regulator uses 10V from the backplane to be operational at boot up. It then controls a power
sequencer to control the power-up of the rest of the circuits on the card.
Each NPU can handle a total of approximately 25 to 30 million packets per second, accounting for
ingress and egress, with a simple configuration. The more packet processing features enabled, the lower
the packets per second that can be processed in the pipeline. This corresponds to up to 15 Gbps of
bidirectional packet processing capability for an NPU. There is a minimum packet size of 64 bytes, and
a maximum packet size of 9 kB (9216) from the external interface. The NPU can handle frames up to
16kB, and the bridge FPGA and fabric interface chip have been designed to handle a frame size of 10kB.
Packet streams are processed by the NPUs and are routed either locally over the Gigabit Ethernet link to
the local CPU or to the RSP fabric card through two bridge FPGAs and the fabric interface chip. The
total bandwidth of the path from four NPUs to two bridge FPGAs is 60 Gbps. The total bandwidth of the
path from the two bridge FPGAs to the fabric interface chip is 60 Gbps. The total bandwidth from fabric
interface chip to the backplane is 46 Gbps redundant. The fabric interface chip connects through four
23 Gbps links to the backplane.
Cisco ASR 9000 Aggregation Services Router Overview and Reference Guide
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D R A F T — C I S C O C O N F I D E N T I A L
General Line Card Data Plane Block Diagram
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Chapter 2 Functional Description
Optics
Optics
Optics
Optics
Timing
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