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DVD-S530/DV-S5550
The spindle-motor interface provides both motor control
signals from the demodulator and, in addition, contains a
tachometer loop that accepts tachometer pulses from the
motor unit. They drive the motor IC (BA6665FM, item
7301).
The SAA7812 has two independent microcontroller
interfaces.
The first is a serial I 2 C-bus and the second is a standard
8-bit multiplexed parallel interface. Both of these
interfaces provide access to 32 8-bit registers for control
and status.
5.2 Interface
The interface between front-end (SAA7812) and back-end
(Sti55xx) is via:
• I2S bus (BCLK, DATA, WCLK, FLAG, SYNC and V4).
• S2B bus (RXD_S2B, TXD_S2B, CPR_S2B and
SUR_S2B).
• Miscellaneous I/O ports (RSTNF= front-end reset,
EANF= front-end processor boot select).
Note: These lines contain series resistors (47 or 100 Ω)
for easy hardware debugging, and for EMC/noise
reduction of the high-speed I2S lines.
The front-end processor SAA7812 (Iguana) has two boot
modes: normal boot from flash memory, or serial mode.
The boot selection is via the EANF pin. The Iguana
samples the EANF signal level once during boot-up. Once
boot-up is completed, this pin is no longer used for this
purpose.
However, in the SD4.0 circuit, the EANF is also connected
to the flash memory. Therefore, when this pin is LOW, the
lower 1Mbits of the memory is accessible. Conversely,
when this pin is HIGH, the upper 1Mbits is accessible.
Under front-end normal operation, the program memory
(less than 1Mbits in size) should reside in the lower bank.
Therefore, the EANF pin should be LOW at all times.
Since the actual flash memory used is 2Mbits, the upper
1Mbits is unused. This area is reserved for possible use by
the front-end self-diagnostic software, or flash download
application.
5.3 Back-End: the Digital Part
The back-end consists of:
• DVD back-end processor.
• External memory.
• Audio output.
• Video output.
• Miscellaneous.
DVD Back-End Processor
The SD4.0 is designed for the Sti55xx family. Some of the
DVD related features of these ICs are:
26
Processor Overview
Function
Basic CD/VCD/DVD decoding
Extra 2-channel of I2S output (PCMDATA3)
Karaoke
DTS
Audio post processing (equalizer, level meter, etc)
DVD audio
Progressive scan at analog video output
Fig. 10
The Sti5580 has the same architecture as the Sti5508
(used in earlier DVD generations), and is pin-to-pin
compatible.
It works on 3.3 V (VDD), and comprises the following
functions:
• Video decoder which supports MPEG1 and MPEG2
• Audio decoder which supports AC-3, MPEG1, MPEG2,
DTS, PCM, S/PDIF, MP3.
• PAL/NTSC video encoder with simultaneously Y/C,
CVBS and RGB/YUV outputs
• The video encoder supports Closed Caption and allows
MacroVision 7.0/6.1
• Full screen On Screen Display (OSD) generator
• Three on-chip PLLs to generate all necessary clocks
(as reference the 27 MHz video clock is used).
Input
Input data comes from the I2S-bus. The front-end
interface of this device, accepts DVD, CD and CD-DA
information.
Signal Processing
For video, the input data stream is decoded to the
appropriate MPEG, Sub Picture, and OSD data streams,
after which they are fed to the PAL/NTSC encoder. This
cell will convert the digital MPEG/Sub Picture/OSD stream
into a standard base band signal and into RGB
components. It handles interlaced and non-interlaced
data, can perform CC/TXT encoding, and allows
MacroVision copy protection.
For audio, the processing cell is a fully compatible DTS,
Dolby Digital (AC-3), MPEG1, MPEG2, and PCM decoder,
capable of decoding 5.1 and 2 channel streams.
Output
For video, six analog output pins are available on which
CVBS, S-VHS (Y/C), and RGB/YUV signals are present.
They go directly to output connector 1701.
STi5580
STi5588
STi5519
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