Ellisys USB Explorer 280 User Manual page 6

7. Link Layer Tests .......................................................................... 50
7.1 Link Bring-Up Test ...................................................................................... 50
7.2 Link Command Framing Test ........................................................................ 53
7.3 Link Command CRC Test ............................................................................. 53
7.4 Invalid Link Command Test .......................................................................... 54
7.5 Header Packet Framing Test ........................................................................ 55
7.6 Data Payload Framing Test .......................................................................... 55
7.7 RX Header Packet Retransmission Test .......................................................... 57
7.8 TX Header Retransmission Test .................................................................... 59
7.9 PENDING_HP_TIMER Deadline Test ............................................................... 61
7.10 CREDIT_HP_TIMER Deadline Test ................................................................. 61
7.11 PENDING_HP_TIMER Timeout Test ............................................................... 62
7.12 CREDIT_HP_TIMER Timeout Test .................................................................. 63
7.13 Wrong Header Sequence Test ...................................................................... 64
7.14 Wrong LGOOD_N Sequence Test .................................................................. 64
7.15 Wrong LCRD_X Sequence Test ..................................................................... 65
7.16 Link Command Missing Test (Upstream Port Only) .......................................... 65
7.17 tPortConfiguration Timeout Test ................................................................... 66
7.18 Low Power Initiation for U1 Test (Downstream Port Only) ................................ 69
7.19 Low Power Initiation for U2 Test (Downstream Port Only) ................................ 70
7.20 PM_LC_TIMER Deadline Test (Downstream Port Only) ..................................... 71
7.21 PM_LC_TIMER Timeout Test (Downstream Port Only) ...................................... 72
7.22 PM_ENTRY_TIMER Timeout Test (Upstream Port Only) .................................... 73
7.23 Accepted Power Management Transaction for U1 Test (Upstream Port Only) ...... 73
7.24 Accepted Power Management Transaction for U2 Test (Upstream Port Only) ...... 74
7.25 Accepted Power Management Transaction for U3 Test (Upstream Port Only) ...... 75
7.26 Transition to U0 from Recovery Test ............................................................. 76
7.27 Hot Reset Detection in Polling Test (Upstream Port Only) ................................ 77
7.28 Hot Reset Detection in U0 Test (Upstream Port Only) ...................................... 78
7.29 Hot Reset Initiation in U0 Test (Downstream Port Only) .................................. 79
7.30 Recovery on Three Consecutive Failed RX Header Packets Test ........................ 80
7.31 Hot Reset Failure Test (Downstream Port Only) .............................................. 81
7.32 Deprecated ................................................................................................ 82
7.33 Exit Compliance Mode Test (Upstream Port Only) ........................................... 82
7.34 Exit Compliance Mode Test (Downstream Port Only) ....................................... 83
7.35 Exit U3 by Reset Test (Downstream Port Only) ............................................... 84
7.36 Exit U3 Test (Host Downstream Port Only) ..................................................... 85
7.37 Packet Pending Test (Upstream Port Only) ..................................................... 86
8. Mass Storage Class Tests ........................................................... 88
8.1 Interface Descriptor Test ............................................................................. 88
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