Transmitter Power Switching Timing Diagram; Synthesizer Clocking - Nokia NSE–3 SERIES Service Manual

PAMS
Technical Documentation

Transmitter power switching timing diagram

Pout
8.3..56.7 us
TXC
TXP
0...56.7 us
TXPWR
150 us

Synthesizer clocking

Synthesizers are controlled via serial control bus, which consists of SDA-
TA, SCLK and SENA1 signals. These lines form a synchronous data
transfer line. SDATA is for the data bits, SCLK is 3.25 MHz clock and
SENA1 is latch enable, which stores the data into counters or registers.
Original 11/97
542.8 us
0...58 us
NSE–3
System Module
50 us
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