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COUNTER
ASSEMBLY
4.114
To
correspond with the delay described
in
the
previous paragraph
the
shift
delay
is
introduced
by IC2a and
IC2b.
The
Q
output of
IC2a and
the
Q
output of
IC2b
are fed
to
the respective
A
and
B inputs of the presettable
decade
counter IC4.
This
inhibits
any
update
of the display data
until
the
next
main
gate period has
been completed.
Trailing Digit
Blanking
4.115
The
trailing digit
blanking
is
achieved by
switching
off
the
anode
supply
to
the
appropriate numerical display LED's.
The
relevant
transistors
are
Q9
and
Q13
which
control these
anode
supplies.
Transistor
Q9
is
switched by
the voltage at the
collector of
Q25
which
is
controlled
by
the
Tune
switch logic
at
input
TCI
via
Q24.
Similarly
Q13
is
switched by
the logic
at
TC2
via
Q23
collector.
Leading
Digit
Blanking
4.
1
16
At
frequencies
below
100MHz
the leading digit
of the display data
is
a zero,
but provision
is
made
for
blanking
this
leading zero
by
applying
a
'low' to
the
ripple
blanking
input
(pin 5)
of the
seven segment decoder
IC9.
The
data
for
this
operation
being obtained from IC3
pins
7 and
9,
encoded by
the
OR
gate
network
IC5a,
b,
c,
d.
4.117
On
the
lowest
frequency range two
leading zeros
will
occur below
10MHz.
The
most
significant digit
on
this
range
is
blanked
off
by applying
the
Range
1
Select
1
logic
to turn off
Q19,
while
the
next most
significant digit
is
blanked
via
IC5
and
19/5
whenever
it
becomes
a zero.
is?'.
\
Complete
Display Blanking
4.118
For
complete
display blanking pin
4
of
IC9 must be held
'low'
.
In
normal
operation both
Q22
and
Q21
are
conducting, giving a
Mow'
at
Q21
collector
and
a
'high' at
IC9/4.
If
the
120MHz
Loop goes out
of lock (para.
4.
93) the
resultant error
signal
applies a
'low
1
via pin 10 of the
Counter p.c.b.
which
turns off
Q22,
and
also
Q21,
thus
applying a blanking
Mow
1
to
IC9/4 which
extinguishes the
whole
display,
thereby
indicating
an
'out
of lock
1
fault.
4.119
A
brief
blanking
pulse
is
applied
at the
end
of
each main
gate period
to
allow
the display
multiplex
to
resynchronise with the
CDI
Chip.
The main
gate
waveform
for this
purpose
is
fed via
inverter
IC6c and
the
trailing
edge
produces
a
narrow
pulse
in
R50,
C21 and
Q21,
which
blanks
the display
for
approximately one
millisecond.
4.120
The
circuitry
of IC7a,
b,
c,
d and IC6b
is
included
in
the
blanking system
for
future
development,
but has no operational function
at present.
9081
&
9082 Vol
.
2
4-22
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