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DIVIDER
AND
PHASE DETECTOR
ASSEMBLY
4.41
The
digit
blanking
is
progressive with both
channel
selection
and range
selection.
When
20,
25
or
60kHz
channel spacing
is
in
use
an
inhibit
is
applied
to
IC2c.
On
50kHz
channel spacing
the inhibit
is
applied
to
IC6b.
When
operating
on one
of the
divided
VCO
ranges
(Range
4
to
Range
2)
however,
the
digit
blanking
is
also
applied
progressively
to
compensate
for
the
frequency
division
which
has
occurred.
For
example
when
Range 4
(120-270MHz)
is
in
use, the
Q1
output from IC4
is
blanked by a
logic signal
applied
via
line
RL,
even though
the
lowest
channel spacing
is
in
use.
Thus
when
a 'divided'
frequency range
is
selected, the
digit
blanking occurs
at
an
earlier
point than
it
would
when
the top
range
(240-540MHz)
is
in
use.
4.42
Digit
blanking
of the
Q2
output
of
IC7
occurs
when
the widest
channel spacing
is
in
use
at the
same
time
as
the
32-64MHz
frequency
range, but
as
IC7
is
a
decade
counter
the associated circuitry
is
more complex.
Range
information
is
provided via
line
RS
and
NOR
gate IC2b.
4.43
When
IC7 reaches
a
count
of ten
the
Q2
outputs
of
IC7 and IC20
change
state.
This
is
detected by
the gating
network IC12a-d.
If
the
Q2
output
of
IC4 goes
to
a
'O'
no
action occurs, but
if
it
changes
to
'1
'
and
the
Q1
of
IC20
is
also a
'1
',
the gating
network
will
force
Q2
of
IC4
back
to
a
'O'
.
HF
Divider
4.44
The Range 4
oscillator signal
is
fed via
socket
SK6
into
the
HF
Divider,
which
is
formed by
the
t
10
or
t
1
1
divider
IC30 feeding
a chain of four
t
2
binaries,
IC29b, IC29a, IC28b
and
IC28a,
all
of
which
are
ECL
packages.
4.45
Divider
IC30 can divide by
either
eleven
or ten, thus
enabling
the particular
circuitry (para.
4.48)
to
divide
by
either 161 or
160.
IC30
divides
by
11
if
pins
2
and
3
(PEI
and
PE2) are both low, but
if
either of these pins
rises
to
logic
'1
',
then
division
by
10
will
occur.
This logic state
is
controlled
by
part of the 'N' divider, as follows.
4.46
Binary divider
IC5
and decade
divider IC9,
with IC8a,
IC1
5a and
associated gates,
form a
swallow counter
with zero detector.
The
output
of the h.f.
divider
is
fed
from
IC28a/2
via
transistors
Ql,
Q6
and
Q
7
to
the
clock
inputs at
IC5/15 and IC9/15.
Each
clock
pulse causes the divider
to
count
down
by one.
4.47
Assume
that
a
count
of
4
is
loaded
into
IC5,
and
IC9
is
at
zero.
Until
a
digital
zero
is
reached
the output of the zero detector
at
IC8q/l remains low,
which
holds
transistor
Q4
non-conducting and
applies a
low
to
IC30/3,
thus
maintaining
r
1 1
mode
in
IC30
and hence
an
overall f 161
mode
in
the h.f. divider.
4.48
When
the
count
in
IC5 reaches zero
this
is
detected
and
IC8a/l goes
high,
which
turns
on
Q4
and
sends
IC30/3
high
thus
changing
the division
ratio
in
IC30
to
10
and
the overall division
to
-f
160.
Thus, division
by
161
lasts
for
the duration of the
count
down
in
IC5/IC9.
The
zero detection
at
IC8q/l
also
turns off
Q7,
which
cuts off the
clock
pulses
from IC5
and
IC9, thus
preventing
any
further
change
in
the h.f. divider
ratio.
4-8
9081
&
9082 Vol
.
2
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