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DIVIDER
AND
PHASE DETECTOR
ASSEMBLY
(a)
Division of the
Range 4
signal
by
a factor 'N'
.
(b)
The
storing of
a
number
'
N', determined by
the
range
and
channel
logic,
which
instructs
the
programmed
divider.
(c)
Phase detection
of
channel spacing data and tuning data
to
provide a
frequency
control (varactor) signal
to
the
main
oscillator,
with
fast
or
slow
response
according
to
tuning
mode.
(d)
A
read-only
memory (ROM)
which,
from channel spacing
and
'N'
counter
data, provides a
(5
octave)
logic
output
which
selects the
appropriate
filter
bandwidths
in
the
Output Assembly.
The
ROM
also
provides 'end
stop
1
logic
to
prevent
the
main
oscillator
from tuning
beyond
the
end
of
each
range.
Note:-
In
model 9082
the extension of the
frequency range
requires
modification
to
the
logic
provided by
the
ROM.
Space
for
the additional circuitry
is
not available
on
the
Divider
and
Phase Detector Assembly,
so
it is
mounted
on
the
Logic
Assembly
(19-0948).
Connections
to
the circuit are
made
via a
24-way
cable
and two
leads
as
shown
in
Figs. 5,
13
and
22.
'N'
Counter
4.38
The
'N' counter
consists of
the binary counter IC4
decade
counter IC7 and binary
counters 1C20,
IC13 and IC23.
The
clock
input
to
the divider
is
a controlled
number
of
300kHz
pulses
from the Logic
Assembly which
is
derived from tuning
(spin
wheel)
information.
The
Up/Down
signal
on
pin
16
of the
p.c.b.
commands
the 'N'
counter
to
count
up
or
down, according
to
the direction
of
tuning.
The
outputs from the 'N'
counter are fed
direct
(or
via the
digit
blanking
gates described
in
succeeding
paragraphs)
to
the data inputs
of IC5, IC9, IC21
,
IC14 and
IC25,
which
operate
in
conjunction with the
h.f. divider.
Digit
Blanking
4.39
The
instrument
always
tunes
to
a
channelized frequency
which
is
determined by
the
channel spacing
selection.
For
example,
the selected
channel spacing could be
the basic
spacing
for
a
group
(e.g.
5kHz)
or
a multiple of
this
spacing
(10kHz
or
20kHz)
.
When
operating on
a
multiple
of the
basic
channel spacing
provision
is
made
for
inhibiting
the
redundant
digit
from
the 'N' counter,
otherwise
the 'N' divider
would
receive
ambiguous
data causing the instrument
to settle
between
channels.
This digit
blanking
is
performed by
the
network
of gates
in
the
Ql, Q2,
Q3
and
Q4
output
lines
from IC4
and
the
Q1
and
Q2
outputs from
1
C
7.
4.40
For
example, assume
that
the
VCO
is
operating on the highest range
and
that
a
basic
channel spacing (5kHz,
6.25kHz
or
15kHz)
is
in
use.
The
pulse input to the
p.c.b.
at pin
15
clocks the binary counter IC4 with a
single pulse
which
provides
an output
pulse via
ICle and
IC
6
a
to
the 'N' divider.
If,
however,
the
first
multiple
of the
channel
spacing
is
in
use (e.g.
10,
12.5
or
30kHz)
IC4
will
be clocked by
two
pulses,
providing
an
output from
Q2
of
IC4
which
is
fed via
IC/a and IC2c
to
the
'N' divider.
Because
the
Ql
output
of
IC4
will
have been clocked back
to
its
original state,
its
data could cause
a
false
offset to
be applied.
It
is
therefore inhibited
by
the closing
of IC
6 a by
the
channel
selection
logic
applied via
R28 and
R29.
4-7
9081
&
9082
Vol
.
2
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