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LOGIC
PCB
ASSEMBLY/
DIVIDER
AND
PHASE DETECTOR
ASSEMBLY
output
at
pin
18,
but
only
for
the
time
that
it
takes
for
!C7a
to reset;
therefore
only
one
300kHz
pulse
will
be allowed
to
pass
for
each
pulse
into
IC7a/3.
4.30
The
effect of introducing
channel spacing
and
range information
will
now
be
considered.
On
all
settings
of the
Channel Spacing
switch
except
Af,
IC15b/4
will
beat
T
level, thus
enabling IClOc
which
allows IC11, IC6
and
IC1
4
to
be
operative.
IC11 introduces
channel spacing data and IC14
introduces
range data.
The two
dividers
operate
in
series.
4.31
Assume
that the
Range
switch
is
set to
the highest
range
and
the
Channel Spacing
switch
to
single
channel
(5kHz
or
6.25kHz).
The
next tuning
spin
wheel
pulse
via
IdOb
clocks
IC7a which changes
the
states
of
IC7a
and IC7b
as
described
in
para.
4.
29.
The
T
at
IC7b/15
is
applied
via
IClOa
to
the preset
enable
of IC11
and
sets
it
to
divide
by'
one.
The Range
switch
line
RA
will
already
have
set
IQS
and IC14
to
divide
by one.
Thus
the
300kHz
allowed
to pass
through
IC9d
will
be
fed
to
the
clock
input at 1C 11/1
5 and
fed
through
to
IC10c/10, without
division,
to reset
IC7a
as
described
in
para.
4.
29.
As
previously described,
only
one
300kHz
pulse
will
be allowed
to
pass
to
pin 18.
4.32
If
the
Channel
Spacing switch
is
set to
a
double channel spacing
(10kHz
or 12
5kHz
•„
f
°
r
example)
IC1
1
wiM
be
set
v?a
IC15d
+2- An
incoming
'tuning'
pulse
from
Cl 0b
will set
IC7a/IC7b
as
previously described,
IC9d
will
be enabled
but
two
300kHz
reference
pulses
will pass to
pin 18 before the
reset
of
IC7a/IC7b
occurs
and
closes
IC9d.
4.33
Similarly, a
channel spacing
selection of
25
will
change
the division
ratio
of
r
cn
l
?
U
t0
.
*
4
'
a,low
'
n 9 four
reference
pulses
to
pass
to
IC14.
A
channel spacing
of 50
will
allow
eight
pulses
to pass,
and
so
on.
4.34
Range
information
is
introduced
by changing
the division ratio of
IC14 by
the
lines
RA,
RB,
RC
and
RD.
For
example, on Range 4 IC14
divides
by
eight.
Thus
a
combination
of
Range 4
with
single
channel spacing (6.25kHz)
will result
in
successive
divisions
by
eight,
giving
an
effective multiplication
by 64.
4.35
Fast
Tune
.
When
FAST
is
selected
on
switch S6, a
'O'
is
applied
to
pin
24 and
via
inverter
IClOd
puts a
'1'
on IC15a, IC15d/13 and IC15c/8
which
effectively
disconnects
the
channel spacing
switch
and
sets
IC11
to
the
maximum
division
ratio
(
-r 8),
thus
giving
the
fastest
tuning
rate.
4.36
On
model 9082
(assembly
19-0948), a
Read
Only Memory (ROM)lC16,
IC's
17
to
24,
Q12
and
resistors
R64
to
68
are
mounted
on
the
Logic
Assembly p.c.b.
This
circuitry
does not form
part of logic circuitry,
and
its
operation
is
described
in
the section
relating
to
the
Divider
and
Phase Detector
Assembly.
DIVIDER
AND
PHASE DETECTOR
ASSEMBLY
19-0846
(9081)
AND
19-0950
(9082)
FIG.
13
Introduction
The
principal functions are
shown
in
the
block diagram
(Fig.
3.2)
at the
end
of
Chapter
3.
These
are
:-
9081
&
9082 Vol
.
2
4-6
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