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COUNTER
ASSEMBLY
Shift
Data
4.107
Reference
to
Table
3
shows
that the
main
gate time
is
decreased by
a factor of
10 as the
Tune
switch
is
moved
from
HOLD
through
SLOW
to
FAST.
The
effect
of
this
would
be
to shift
the display
one
place
to
the
right for
each
switch
movement
were
it
not
counteracted
by
providing
an
equivalent
shift
to
the
left.
This
is
done by changing
the
reset
point
in
the
counter IC4
as follows:-
HOLD
mode
.
.
.
reset to
'0'
SLOW
mode
.
.
.
reset to
T
FAST mode
.
.
.
reset to
'2'
The
reset
is
determined by
the
shift
data applied
to
pins
4 and
10 of IC4.
TABLE
3
COUNTER
ASSEMBLY DATA
Tune
Control
Time
Base
Control
Code
x
y
z
Display
Shift*
Ratio
Multiplier
10
n
Binary
Multiplier
2
r
Time
Base
Input Freq
1MHz
2
r
(B)
Main
Gate
Time
ms
Counter
Input Freq
MHz(A)
Carrier
Freq
Range
MHz
1MHz
n
1
5-32
5-32
F
2
2
500kHz
2
32-64
A
c
1
1
0
to
10 3
4
250kHz
16-32
64-128
J
T
left
8
125kHz
8
128-256
16
62.5kHz
16
256-512
1
1
MHz
10
5-32
+
5-32
+
S
1
2
500kHz
20
32-64
L
O
W
0
0
1
to
1
0
4
|
4
250kHz
40
16-32
64-128
left
8
125kHz
80
128-256
16
62.5kHz
160
256-512
1
1
MHz
100
mssm
H
No
2
500kHz
200
32-64
O
L
D
1
0
1
Shift
10
5
4
250kHz
400
16-32
64-128
8
125kHz
800
128-256
16
i
62.5kHz
[,"
'
1
1600
256-512
*
Display
shift
is
described
in
para.
4.107.
+
1.5-32
for
model 9082.
4-20
9081
&
9082 Vol
.
2
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