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DV-NC55U/C/M
11-7. IC602-3 IX3455CE 16M SDRAM
Pin No.
Terminal Name
35
CLK
34
CKE
18
CS
19
BS
20~24
A0~A10
27~32
17, 16, 15
RAS, CAS, WE Row Address Strobe,
14, 36
DOML, DOMU
2, 3, 5,
I/O0~15
6, 8, 9, 11, 12, 39, 40,
42, 43, 45, 46, 48, 49
VCC/VSS
1, 25, 26
4, 7, 10,
VCCO/VSSO
13, 38, 41, 44, 47, 50
33, 37
NC
• Block Diagram
Refresh
Interval Timer
Address[0:10]
CLK
CKE
BS(A11)
CS
RAS
CAS
WE
DOMU
DOML
Name
Clock
The system clock input. All other inputs are referenced to the SDRAM on
the rising edge of CLK.
Clock Enable
Controls internal clock signal and when deactivated, the SDRAM will
be one of the states among power down, suspend or self refresh.
Chip Select
Command input enable or mask except CLK, CKE and DOM
Bank Address
Select either one of banks during both RAS and CAS activity.
Address
Row Address: RA0~RA10, Column Address: CA0~CA7
RAS, CAS and WE define the operation.
Column Address Strobe,
Refer function truth table for details.
Write Enable
Data Input/Output Mask
DOM control output buffer in read mode and mask input data in write mode.
Data Input/Output
Multiplexed data input/output pin
Power Supply/Ground
Power supply for internal circuit and input buffer.
Data Output Power/Ground Power supply for DO
No Connection
No connection
Self Refresh Counter
Refresh
Counter
Address
Precharge
Register
Row Active
Column Active
Burst Length
Counter
Mode Register
Input Function
512Kx16
Bank 0
Sense AMP & I/O gates
Column Decoder
Column Addr.
Latch & Counter
Overflow
Column Decoder
Sense AMP & I/O gates
512Kx16
Bank 1
Test Mode
64
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I/O Control
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