Sharp DV-NC55U Service Manual page 61

Name Type
Host interface, CD-DSP interface, sub-code interface (32-pin)...continued
HRDY O(p.d.)
HIRQ# O(p.u.)
HACK# O(p.u.)
GPI/O signal (3-pin)
GPIO I/O(r.t.)
GPSI I
GPSO O(p.d.)
PLL signal (5-pin)
GCLK ID
GCLK1 ID
XO AO
PLLCFG[1:0] ID
Analog video port (7-pin)
CVBS/G/Y
AO
(DAC A)
Y/R/V
AO
(DAC B)
C/B/U
AO
(DAC C)
CVBS/C
AO
(DAC D)
RSET AI
VREF AI
COSYNC O(p.d.)
Digital video port (5-pin)
VCLKx2 I/O(r.t.)
VCLK I/O(r.t.)
HSYNC I/O(r.t.)
VSYNC I/O(r.t.)
FI I/O(r.t.)
Host ready output (active High). Use this signal when the stream is transferred via
the host bus. External pull-up resistor is required. Prior to transfer of each packet (1
packet: length in CodBurstLen bytes), make sure that this signal is in the active state,
and then bit streams of CodBurstLen byte long or shorter can be written on this device
consecutively.
Interrupt request (active Low). This is deasserted when the host reads the interrupt
status register of this device and also when the host masks or resets the interrupt
using the interrupt mask register.
When HIRQ# is not asserted, it enters the 3-state mode. (External pull-up resistor is
required.)
Host acknowledge output (active Low). When the protocol is A type, the device asserts
this output and notifies the completion of read or write cycle.
When this signal is not active, it enters the 3-state mode. (External pull-up resistor is
required.) When the protocol is B type, this signal functions as a wait output signal. If
the high-speed host (microcomputer) is used, this signal may not have to be connected.
General-purpose bidirectional pin monitored and controlled by the ADP micro code.
After resetting, this pin is defined as an input. It can be set by using the ADP command.
General-purpose input monitored by the DVP micro code.
General-purpose output controlled by the DVP micro code. After resetting, output
from this pin is switched to Low.
27,000 MHz clock or crystal input for main processor.
27,000 MHz master clock input for audio. Normally, this must be connected to GCLK.
Output to crystal connected to GCLK. If the crystal is not used for GCLK, nothing
must be connected to XO.
PLL configuration input. It can be changed only during resetting. Normally, both pins
must be connected to GNDP.
For CVBS, the composite video signal is output.
For RGB, the G signal is output.
For YUV, the Y signal is output.
For CVBS, the Y signal is output.
For RGB, the R signal is output.
For YUV, the V signal is output.
For CVBS, the C signal is output.
For RGB, the B signal is output.
For YUV, the U signal is output.
The CVBS or C signal is selected and output.
Resistance load for DAC gain adjustment is inserted between GND and DAC.
Reference voltage for DAC gain adjustment is input.
Composite sync output. Effective only when the RGB analog output is selected.
Otherwise, it is fixed to Low.
Main video clock input or output. 27,000 MHz.
Divided VCLKx2 signal. Used as a qualifier of data and sync signal.
Horizontal sync bidirectional signal pin. Its polarity and length are programmable.
Vertical sync bidirectional signal pin. Its polarity and length are programmable.
Field identification bidirectional signal pin. Its polarity is programmable.
61
Description
DV-NC55U/C/M