Sharp DV-NC55U Service Manual page 62

DV-NC55U/C/M
Name
Digital audio port (8-pin)
AMCLK
S/PDIF (AOUT[3])
AOUT[2:0]
AIN
ALRCLK
ABCLK
DVD-DSP interface (13-pin)
DVDREQ
DVDVALID
DVDSOS
DVDDAT[7:0]
DVDSTRB
DVDERR
SDRAM interface (35-pin)
RAMDAT [15:0]
RAMADD [11:0]
RAMRAS#
RAMCAS#
PCLK
RAMDQM
RAMCS0#
RAMCS1#
RAMWE#
TEST signal (pin 3)
SCNENBL
TESTMODE
ICEMODE
Power signal (49-pin)
GNDP
VDDP
VDDIP
GNDAAM
VDDAAM
GNDC
VDDC
GNDA
VDDA
VDDD
GNDDAC
[D,B,P,S]
Type
Audio master clock I/O. Sampling frequency can be selected among 384fs, 256fs,
I/O(p.u.)
192fs, and 128fs (programmable).
S/PDIF transmitter output. It can be connected to DAC as the fourth audio output
O(p.d.)
(AOUT [3]). After resetting, this pin outputs the low-level signal.
Serial output of PCM stereo audio for DAC. After resetting, this pin outputs the low-
O(p.d.)
level signal.
I Serial input of PCM stereo audio for ADC.
LR clock output of AOUT [4:0] and AIN. The square wave is formed with the sampling
O(p.d.)
frequency. The LR polarities are programmable.
Bit clock output of AOUT [4:0] and AIN. AOUT is output to this clock in the leading
O(p.d.)
and trailing edges (programmable) and AIN is latched.
O(p.d.) DVD-DSP data request output (polarity programmable).
I DVD-DSP data effective input (polarity programmable).
I DVD-DSP data sector start input (polarity programmable).
I DVD-DSP data input bus.
ID DVD-DSP data bit strobe (clock) input. Polarity programmable.
I DVD-DSP error input. Polarity programmable.
I/O(r.t.) SDRAM bidirectional data bus.
O(p.d.) SDRAM address bus output.
O(p.u.) SDRAM row selection (active Low) output.
O(p.u.) SDRAM column selection (active Low) output.
O(p.d.) SDRAM clock output (same as the internal processing clock).
O(p.d.) SDRAM data masking (active High) output.
O(p.u.) SDRAM chip select (active Low) output. Lower 2 Mbyte device.
O(p.u.) SDRAM chip select (active Low) output. Upper 2 Mbyte device.
O(p.u.) SDRAM write enable (active Low) output.
ID Test pin. Normally connected to GNDP.
ID Test pin. Normally connected to GNDP.
ID Test pin. Normally connected to VDDP.
S Ground for 3.3V digital power supply.
S 3.3V digital power supply
S 3.3V digital power supply
S Ground for PLL power supply for 3.3V AMCLK generation.
S PLL power supply for 3.3V AMCLK generation.
S Ground for 1.8V digital power supply.
S 1.8V digital power supply.
S Ground for PLL power supply for 1.8V internal clock generation.
S PLL power supply for 1.8V internal clock generation.
S Analog power supply for 3.3V video DAC.
S Ground for Analog power supply for 3.3V video DAC.
Description
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