Award Bios Post Codes - ROHS EmCORE-i2702 User Manual

3.14 Award BIOS POST Codes

CFh Test CMOS read/write functionality
C0h Early chipset initialization:
and below), program basic chipset registers
C1h Detect memory:
detection of L2 cache (socket 7 and below)
Ch Expand compressed BIOS code to DRAM
Ch Call chipset hook to copy BIOS back to E000 & F000 shadow RAM
01h Expand the Xgroup codes located in physical memory address 1000:0
02h Reserved
0h Initial Superio_Early_Init switch
0h Reserved
0h Blank out screen; Clear CMOS error flag
06h Reserved
07h Clear 802 interface; Initialize 802 self test
Test special keyboard controller for Winbond 977 series Super I/O
08h
chips; Enable keyboard interface
09h Reserved
Disable PS/2 mouse interface (optional); Auto detect ports for keyboard
0Ah & mouse followed by a port & interface swap (optional); Reset keyboard
for Winbond 977 series Super I/O chips
0Bh Reserved
0Ch Reserved
0Dh Reserved
Test F000h segment shadow to see whether it is read/write capable or
0Eh
not. If test fails, keep beeping the speaker
0Fh Reserved
Auto detect flash type to load appropriate flash read/write codes into
10h
the run time area in F000 for ESCD & DMI support
11h Reserved
Use walking 1's algorithm to check out interface in CMOS circuitry. Also
12h
set real time clock power status and then check for overrride
1h Reserved
Program chipset default values into chipset. Chipset default values are
1h
MODBINable by OEM customers
1h Reserved
16h Initial Early_Init_Onboard_Generator switch
17h Reserved
Detect CPU information including brand, SMI type (Cyrix or Intel) and
18h
CPU level (86 or 686)
19h Reserved
1Ah Reserved
Initial interrupts vector table. If no special specified, all H/W interrupts
1Bh are directed to SPURIOUS_INT_HDLR & S/W interrupts to SPURIOUS_
soft_HDLR
1Ch Reserved
1Dh Initial EARLY_PM_INIT switch
1Eh Reserved
1Fh Load keyboard matrix (notebook platform)
Disable shadow RAM, L2 cache (socket 7
Auto detection of DRAM size, type and ECC, auto
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BIOS