Block Diagram - pro bel V6402 HD User Manual

V6402, V6404, V6406, V6408
and V6418 HD converters
1.2

Block Diagram

LVDS Misc I/O (Clk, F, RxD, TxD, etc.)
LVDS Video Out (3 pairs Data + 1 pair Clock)
LVDS Video In (3 pairs Data + 1 pair Clock)
I/O Daughter Card
Cable Driver
Reclocked HD Output
HD SDI Input1
Cable EQ
HD SDI Input2
Cable EQ
Tri-Le vel Sync or
Black & Burst
Reference Input
H
Sync Separator V
F
Loop Through Ref.
Ext. Flash
Hitachi
'Beagle'
H8S/2633
CPLD
'41 Style Front Panel
Control & Status Indication
14.7456MHz
System Control Interface (DART)
Ref Data EEProm
&
I2C Interface
HU-V6402&4&6&8&18
V6402 / V6404 / V6408 / V6418
Input CLK
Reclocker
20-Bit YUV
&
De-Serializer
VCO
20-Bit YUV
Ref H
Genlock Ref V
PLL Ref F
Clock-Generator Ref CLK27
Ref CLK74
27MHz
Serial Control Bus
Internal I2C
21-Bit LVDS Rx 21-Bit LVDS Tx
F
Ref CLK74
FPGA
Output CLK
Serial Control
Frame-Sync
TPG
30-Bit RGB or 10-Bit YUV (muxed)
Audio De-Embedding
Ref CLK27 Audio Re-Embedding Scaler Output CLK
(84-Bit wide optional)
SDRAM
Ref CLK74 Frame Store Options:
2M x 32
16MByte Min (2x 2Mx32)
96MByte Max (3x 8Mx32)
SDRAM SDRAM
2M x 32 2M x 32
Serial Control
Ref CLK A
IN_CLK
CLKOUT
Ref CLK74
PRC_C LK
Ref CLK B
OUT_C LK
2D Scaler
Down- & Cross-
Converter Option
(not fitted on V6402)
SDRAM SDRAM
2M x 32 2M x 32
I/O Daughter Card
Asynchronous Serial Comms Port
between H8's on V640x and V6302 Cable Driver
Multi-Rate
20-Bit YUV
Serializer
VCO
Clock Distribution
Ref CLK A
Ref CLK74 Ref CLK A
Ref CLK A
Ref CLK27 Ref CLK A
Ref CLK B
Ref CLK27 Ref CLK B
Ref CLK B
Ref CLK74 Ref CLK B
JTAG
3.3V, 1.8V, 1.5V
Power Supplies
SD SDI Output1
SD SDI Output2
DLY Pulse Output
74/27MHz Clock
27/74MHz Clock
7