Post Code Checkpoints - ROHS EmETXe-i9652 User Manual

BIOS

3.9.3 POST Code Checkpoints

The POST code checkpoints are the largest set of checkpoints during
the BIOS pre-boot process. The following table describes the type of
checkpoints that may occur during the POST portion of the BIOS
Checkpoint
Disable NMI, Parity, video for EGA, and DMA controllers.
Initialize BIOS, POST, Runtime data area. Also initialize BIOS
03
modules on POST entry and GPNV area. Initialized CMOS as
mentioned in the Kernel Variable "wCMOSFlags."
Check CMOS diagnostic byte to determine if battery power
is OK and CMOS checksum is OK. Verify CMOS checksum
manually by reading storage area. If the CMOS checksum is
04 bad, update CMOS with power-on default values and clear
passwords. Initialize status register A. Initializes data variables
that are based on CMOS setup questions. Initializes both the
8259 compatible PICs in the system
Initializes the interrupt controlling hardware (generally PIC)
05
and interrupt vector table.
Do R/W test to CH-2 count reg. Initialize CH-0 as system
timer.Install the POSTINT1Ch handler. Enable IRQ-0 in
06
PIC for system timer interrupt. Traps INT1Ch vector to
"POSTINT1ChHandlerBlock."
07 Fixes CPU POST interface calling pointer.
Initializes the CPU. The BAT test is being done on KBC.
08 Program the keyboard controller command byte is being done
after Auto detection of KB/MS using AMI KB-5.
C0 Early CPU Init Start -- Disable Cache – Init Local APIC
C1 Set up boot strap processor Information
C2 Set up boot strap processor for POST
C5 Enumerate and set up application processors
C6 Re-enable cache for boot strap processor
Description
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(Note)