VIORE PDP4210EA Service Manual page 62

HDCP Decryption Engine and XOR Mask
The HDCP decryption engine contains all the necessary logic to decrypt an incoming video signal on a pixel-by-
pixel basis. The host system microcontroller initiates an authentication sequence with the receiver to initialize the
SiI 169 HDCP decryption engine. Upon successful completion of the authentication process, the SiI 169 is ready
to decrypt the incoming video via the XOR mask.
Encrypted and unencrypted video will be sent at different times. Therefore the host HDCP transmitter uses the
CTL3 signal to indicate to the SiI 169 receiver whether the incoming video is encrypted or not.
HDCP Keys EEPROM
The SiI 169 comes pre-programmed with a production set of HDCP keys in its internal EEPROM. In this way the
keys are provided the highest level of protection as required by the HDCP specification. Silicon Image manages all
aspects of the key purchasing and programming. There is no need for the customer to purchase HDCP keys from
the licensing authority. For security reasons, the keys cannot be read out of the device.
Samples of the SiI 169 are available with the B1 public keys as listed in the back of the HDCP specification.
These are marked with a -PUB part number as noted in the Ordering Information section. Make sure to request
either "Public" or "Production" keys when requesting samples. Before receiving samples of the SiI 169 with
production keys a customer must have signed the HDCP license agreement.
Panel Interface Logic and Configuration Logic
Unencrypted video data is sent to the display logic by way of a 48-bit output interface. The functionality of this
interface is affected by several of the externally strapped configuration logic options as follows.
•
The data output can be presented in either one pixel per clock or two pixels per clock format, depending on
the PIXS configuration setting.
• The polarity of the output clock ODCK can be inverted to accommodate both rising- and falling-edge clocking
through the OCK_INV configuration setting.
• Using the STAG_OUT configuration setting, the odd and even data output groups can be staggered in time to
reduce EMI.
•
The HS_DJTR configuration setting can compensate for host-side jitter on the HSYNC input to the transmitter.
•
The PD# and PDO# inputs select chip power down modes and allow for disabling of the outputs to the panel.
The RESET# input must be in the HIGH state during normal operation, in both HDCP and non-HDCP modes. Its
primary purpose is to reset the digital block circuitries, including the HDCP engine, and registers at initial chip
power-up time. The VSYNC, HSYNC, DE, and CTL3 signals will be driven low while RESET# is asserted.
necessary to disable the HDCP engine while leaving the chip fully operational for reception of unencrypted video, use the
software reset feature located at bit 0 of register 0xFF by setting it to "1".
SiI-DS-0049-B
3
SiI 169 HDCP PanelLink Receiver
Data Sheet
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