VIORE PDP4210EA Service Manual page 61

SiI 169 HDCP PanelLink Receiver
Data Sheet
Functional Description
The SiI 169 is a DVI 1.0 compliant digital-output receiver with built-in High-bandwidth Digital Content Protection
(HDCP). It provides a simple, cost effective solution for DTVs implementing DVI-HDCP. Pre-programmed HDCP
keys simplify manufacturing while providing the highest level of security. There is no need to use encrypted keys,
program EEPROMs, or cure epoxy coating.
Figure 2 shows the functional blocks of the chip.
SCLS
SDAS
RXC±
RX0±
RX1±
RX2±
EXT_RES
PanelLink TMDS Core
The PanelLink TMDS core accepts as inputs the three TMDS differential data lines and the differential clock. The
core senses the signals on the link and properly decodes them providing accurate pixel data. The core outputs
the necessary sync signals (HSYNC, VSYNC), clock (ODCK), and a display enable (DE) signal that drives high
when video pixel data is present. The SCDT signal is output when there is active video on the DVI link and the
PLL has locked on to the video. SCDT can be used to trigger external circuitry, indicating that an active video
signal is present; or used to place the device outputs in power down when no signal is present (by tying SCDT to
PDO#). A resistor tied to the EXT_RES pin is used for impedance matching.
2
I C Interface and Registers
The SiI 169 uses a slave I
authentication is managed by reading and writing to registers through the I
the DVI specification, is also tied to the EDID EEPROM that contains information about the display's capabilities
(resolution, aspect ratio, etc.). The I
5V tolerant and it is recommended that a voltage level shifter be used between the SiI 169 and the DVI connector
as the DDC bus is specified to support 5V signaling.
Registers
--------------
Configuration Logic
2
I C
Slave
PanelLink
24
TM
TMDS
/
encrypted
Digital
data
Core
Figure 2. Functional Block Diagram
2
C interface, capable of running at 400kHz, for communication with the host. HDCP
2
C address of the SiI 169 is 74h as specified by HDCP. This interface is not
HDCP
Decryption
Engine
XOR 24
/
Mask
unencrypted
data
control
2
C interface. This bus, called DDC in
2
HDCP
Keys
EEPROM
CTL3
QE[23:0]
QO[23:0]
Panel
ODCK
Interface
Logic DE
HSYNC
VSYNC
SCDT
SiI-DS-0049-B