Philips LC4.3E Service Manual page 64

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Circuit Diagrams and PWB Layouts
IBO Zapper: Mojo
1 2
MOJO
K1
A
K1, K2, k7 MIU_WEN
K2 NOR_RYBY
B
RESET_n
K2, K3
4MHz_MOJO
K6
C
D
7100-2
PNX8316HS
(TS)
E
TS_DATA(0)
K7 2V2 20
0
TS_DATA(1)
K7 2V2 21
1 TS_SYNC
TS_DATA(2)
K7 2V2 22
2
TS_DATA(3)
K7 2V2 23
3 TS_DATA TS_STROBE
TS_DATA(4)
K7 2V2 24
4
K7 TS_DATA(5) 2V2 25
5 TS_VAL
TS_DATA(6)
K7 2V2 26
6
TS_DATA(7)
K7 2V2 27
7
7100-3
PNX8316HS
F
1V 202
K5 MOJO_I2S_OUT_SD
SD_OUT
3135 22R (AV)
K5 MOJO_I2S_OUT_SCK 0V 203
SCK_OUT
3134 22R
1V6 204
K5 MOJO_I2S_OUT_WS
WS_OUT
3133 22R
K4
SPDIF 206
SPDIF
3142 100R
3164
K5 205
MOJO_SYSCLK
FSCLK
G
22R
I2C_LOCAL_SCL
K2, K6, K7
K2, K6, K7 I2C_LOCAL_SDA
K5 I2C_TV_SCL F135
H
3
OPTION
4101
F136
K5 I2C_TV_SDA
3 2
7104
BSN20
1
+3V3_MOJO
OPTION
K4 USB_OVRCUR
K4 USB_PWR
K4 USB_DM
USB_DP
K4
3139 123 5906.2
1 2
LC4.3E AB
3 4 5 6
3114 RES
10K 3119 10K
3115 10K
3138 RES
10K
3116 10K
3117
10K
3100
10K
4102
4104
+1V2_MOJO
5103
100MHz
1V2clean
2133
10u
PCST0_0
TS_SYNC
30 0V K7 PCST0_1
DSU_CLK
TS_CLK
29 1V6 K7 PCST0_2
28 1V3 TS_VALID K7
FOR DEV. ONLY
5101
+1V2_MOJO
168
100MHz
CVBS
2100
Y 5102
0V C_CVBS K5 10u
172
100MHz
C
CVBS
2101
170
Y
10u
CVBS
B|Pb K5
0V
163 2102
B
G|Y
K5 10u
165 0V
G
Y
R|Pr K5
167 0V
R
C
F133
3143 100R
F134
3144 100R
7100-6
4100 PNX8316HS
(I2C-USB-SCO)
4V6 6
SCL0
2 37
SC0_CMDVCC
7103 4V6 7
SDA0
BSN20
199
I100 USB_PWR
3146 100R 3V3 8
SCL1
200
1 +3V3_MOJO USB_DP
I101
100R 3V3 9
3147
SDA1
201
USB_DM
36
OPTION SC0_DA
40
SC0_CCK
198
USB_OVRCUR
38
SC0_RST
39
SC0_OFF
+3V3_MOJO +3V3_MOJO
3 4 5 6
7. 64
7 8 9
F105 MOJO_TRST F138
1 2
F108
MOJO_TDI 3 4
F114
10046_TDO 5 6
F109
MOJO_TMS 7 8
F111
MOJO_TCK 9 10
F106
RESET_n 11 12
F107
PCST0_0 13 14
F110
PCST0_1 15 16
F112
PCST0_2 17 18
F113
DSU_CLK 19 20
1101
FTR
FOR DEV.
CONFIGURABLE
JTAG_TCK ONLY
4105
4110 JTAG_TRST
4106 JTAG_TMS
4107 STV_TDI
F125
10046_TDO
4109
2122
3113
RES RES
FTSH-114-01-L-DV
ROW_1
ROW_2
1100-1 1100-2
MOJO_TRST 1
2
MOJO_TDI 3
4
10046_TDO 5
3101 6
MOJO_TMS 7
8
MOJO_TCK 9 +3V3_MOJO
10K 10
RESET_n 11
12
PCST0_0
13
14
PCST0_1
0V 15
16
0V PCST0_2 17
18
0V DSU_CLK 19
20
21
22
TPCI 23
24
25
26
0V
PCST1_0 27
28
0V PCST1_1 FTSH-114-01-L-DV
0V PCST1_2
7100-1
1V2
1V2_CORE PNX8316HS
2112 100n 41 42
2113 100n 78 (PWR) 79
2114 100n 119 VDDC VSSC 120
2115 100n 134 135
2116 100n 191 192
3V3
2103 100n 10 11
100n
2104 43 44
2105 100n 60 61
100n
2106 76 77
2107 100n 94 95
VDDP VSSP
2108 100n 111 112
2109 100n 130 131
100n
2110 161 162
2111 100n 190 193
+3V3clean
175 2119
2132 0
100n
169 2120
10u 16V AVDD 1
100n
164 2121
2131 2
100n
171
10u 16V 1
IDUMP
166
2130 2
I105
174
10u 16V
1V2
173
+3V3_MOJO
+3V3
7 8 9
10 11 12 13
7100-4
PNX8316HS
0V
0V 113 (SDRAM) 153
K2 SDRAM_DATA(0)
0 0
0V
K2 SDRAM_DATA(1) 2V6 114 154
1 1
2V6 115 155 0V
K2 SDRAM_DATA(2)
2 2
2V6
K2 SDRAM_DATA(3) 116 156 0V
3 3
K2 2V6 117 149 0V
SDRAM_DATA(4)
4 4
K2 SDRAM_DATA(5) 2V6 118 148 0V
5 5
0V
K2 0V 121 147
SDRAM_DATA(6)
6 6
SDRAM_ADDR
0V
K2 SDRAM_DATA(7) 2V3 122 146
7 7
K2 2V9 132 145 0V
SDRAM_DATA(8)
8 SDRAM_DATA 8
K2 SDRAM_DATA(9) 2V5 129 144 0V
9 9
0V
K2 0V 128 152
SDRAM_DATA(10)
10 10
2V5 0V
K2 SDRAM_DATA(11) 127 143
11 11
K2 2V3 126 142 0V
SDRAM_DATA(12)
12 12
K2 0V
SDRAM_DATA(13) 2V3 125 150
13 13
K2 0V 124 151 0V
SDRAM_DATA(14)
14 14
2V1
K2 SDRAM_DATA(15) 2V3 123 138
15 DQM0
3V1
133
DQM1
140 3V
CAS
141 2V9
RAS
3V
139
WE
3V3
137
CKE
1V5
136
HSCKB
7100-7
PNX8316HS
K6 RESET_FE_n
3V3
31
IR_IN
(GPIO)
K7 RESET_STV 0V
32
IR_OUT
K2 user_EEPROM_WP 4V6
185 17 0V
PWM DTR0
VS VCXO_CLOCK
dsp_EEPROM_WP
K6 UART1_RX
3V3 33 18 0V
VPP RX1
K6 FE_LOCK
3V3 34 19 3V3 UART1_TX
C4 TX1
K2 NOR_RYBY
0V 35
C8 BOOT <0:3>
NOR_WP
K2 0V
0V PIO19|ITU_OUT0|BOOT0
45 176
SC1_DA 0
STV_INT
K7 0V
46 177 3V3 PIO20|ITU_OUT1|BOOT1
SC1_CMDVCC 1
STV_A25
K7 0V 3V3 PIO21|ITU_OUT2|BOOT2
47 178
SC1_RST 2
DSW_n 3V3
48 179
SC1_OFF 3
PIO22|ITU_OUT3|BOOT3
RS232_DSR ITU_OUT
0V I103
49 180
SC1_CCK 4
0V
CTSN0 12 181 3V2
CTS0 5
0V
RTSN0
13 182
RTS0 6
F132
0V
K4 RXD0 14 183
RX0 7
0V
0V
K4 TXD0
15 184
TX0 ITU_CLOCK
+3V3_MOJO
0V
DCD0 16
DCD0 PIO <16:27>
3151
PLL_OUTX0
RES 10K
PIO <0:15>
DSW_I2C_enable
10K
7100-5
3154
PNX8316HS
K2, K7 33R
MIU_DATA(0) 3157-1 69 0V 75 0V
0 0
3157-3
K2, K7 MIU_DATA(1) 8 1 33R 67 (MIU) 80
0V 3V3
1 1
3158-1
K2, K7 MIU_DATA(2) 6 3 33R 65 0V 81 0V
2 2
3158-3 8 33R
K2, K7 MIU_DATA(3) 1 63 0V 82 3V3
3 3
K2, K7 MIU_DATA(4) 3156-1 6 3 33R 59 0V 83 3V3
4 4
3156-3
K2, K7 MIU_DATA(5) 8 1 33R 57 84 3V3
0V
5 5
3159-1
K2, K7 MIU_DATA(6) 6 3 33R 55 0V 85 3V3
6 6
3159-3 33R
K2, K7 MIU_DATA(7) 8 1 53 0V 86 0V
7 7
K2 3157-2 6 3 33R
MIU_DATA(8) 68 0V MIU_DATA 87 0V
8 8
K2 MIU_DATA(9) 3157-4 7 2 33R 66 88 3V3
0V
9 9
K2 MIU_DATA(10) 3158-2 5 4 33R 64 0V 89 0V
10 10
3158-4 33R
K2 MIU_DATA(11) 7 2 62 0V 90 0V
11 11
3156-2 33R 3V3
K2 MIU_DATA(12) 5 4 58 0V 91
12 MIU_ADDR 12
K2 MIU_DATA(13) 3156-4 7 2 33R 56 92 0V
0V
13 13
3159-2
K2 MIU_DATA(14) 5 4 33R 54 0V 93 3V3
14 14
3159-4 33R
K2 MIU_DATA(15) 7 2 52 0V 96 0V
15 15
5 4 97 0V
16
MIU_RDY
K7 3V3 109 98 3V3
MIU_RDY 17
99 3V3
18
K2 NOR_CS 3V3 74 100 3V3
MIU_CS_N0 19
101 3V3
3160 20
K7 STV_CS 73 102 3V3
3V3
MIU_CS_N1 21
103 0V
33R 22
72 104 0V
MIU_CS_N2 23
105 0V
24
71
MIU_CS_N3
107
MIU_MASK1
3161
K2, K7 MIU_OEN 3V3 70
MIU_OE_N
110
33R
MIU_LBA
MIU_WEN
K2, K7 3V3 108
MIU_WEN
50
3162 MIU_BAA
106
33R
MIU_MASK0
51
MIU_CLK
10 11 12 13
It`s Free
14
1100-1 D8 7104 H2
1100-2 D8 7105 F13
1101 B9 F105 A7
SDRAM_ADDR(0) 1106 D14 F106 A7
K2
2100 F6 F107 A7
SDRAM_ADDR(1) K2
2101 F6 F108 A7
2102 G6 F109 A7
SDRAM_ADDR(2)
K2
2103 G6 F110 A7
A
SDRAM_ADDR(3) K2 2104 G6 F111 A7
2105 G6 F112 A7
SDRAM_ADDR(4)
K2
2106 G6 F113 A7
2107 G6 F114 A7
SDRAM_ADDR(5) K2
2108 H6 F122 E9
SDRAM_ADDR(6) 2109 H6 F125 B6
K2
2110 H6 F129 E13
SDRAM_ADDR(7) K2
2111 H6 F131 E13
2112 F6 F132 F13
SDRAM_ADDR(8)
K2
2113 F6 F133 G3
SDRAM_ADDR(9) K2 2114 F6 F134 H3
2115 G6 F135 H2
SDRAM_ADDR(10)
K2
2116 G6 F136 H2
2119 H9 F137 F14
SDRAM_ADDR(11) K2
B
2120 H9 F138 A10
SDRAM_ADDR(12) K2 2121 H9 I100 H4
2122 C8 I101 H4
SDRAM_ADDR(13) K2
2130 I7 I103 F13
2131 I7 I104 E6
SDRAM_ADDR(14) K2
2132 H7 I105 I9
SDRAM_DQM0
K2 2133 C5
3100 A4
SDRAM_DQM1
K2
3101 E6
3112 E9
SDRAM_CAS
K2
3113 C7
SDRAM_RAS
K2 3114 A3
C
3115 A4
SDRAM_WE
K2
3116 A4
SDRAM_CKE 3117 A4
K2
3119 A4
SDRAM_CLK
K2 3120 E5
3121 E5
3122 E6
3123 E6
3124 E6
3125 E6
3126 E6
D 3127 E6
3128 E14
3141 3129 F14
3130 E14
10K
3131 E14
3132 F14
1106
B2B-PH-K
3133 G1
F129
3134 G1
1
3135 F1
F131 2
3136 E14
3137 F14
OPTION
3138 A3
3130 10K E
3139 C6
10K 3140 I9
3128
+3V3
3141 D14
3131 10K
+3V3 3142 G1
OPTION 3143 G4
3136 10K
3144 H4
3129 10K 3145 H2
+3V3
3146 H4
OPTION
3137 10K
3147 H4
4108
3148 I2
F137
TV_IRQ 3149 I3
K5
2 3 3150 I3
F
7105
3151 F13
BSN20
3132 3154 G13
10K
1
3155 G14
OPTION 3156-1 G11
3156-2 H11
+3V3
3156-3 G11
3156-4 H11
3155 3157-1 G11
+3V3
3157-2 H11
10K
RES 3157-3 G11
3157-4 H11
G 3158-1 G11
3158-2 H11
MIU_ADDR(0) K2, K7
3158-3 G11
MIU_ADDR(1) K2, K7
MIU_ADDR(2) K2, K7 3158-4 H11
MIU_ADDR(3) K2, K7 3159-1 G11
MIU_ADDR(4)
K2, K7
3159-2 H11
MIU_ADDR(5)
K2, K7
3159-3 H11
MIU_ADDR(6)
K2, K7
3159-4 H11
MIU_ADDR(7) K2, K7
3160 I11
MIU_ADDR(8) K2, K7
MIU_ADDR(9) K2, K7
3161 I11
MIU_ADDR(10) K2, K7
3162 I11
MIU_ADDR(11) K2, K7
3163 G11
MIU_ADDR(12) K2, K7
H
3164 G1
MIU_ADDR(13)
K2, K7
MIU_ADDR(14) K2, K7 4100 H3
MIU_ADDR(15) K2, K7
4101 H2
MIU_ADDR(16) K2, K7
4102 A4
MIU_ADDR(17) K2, K7
4104 A4
MIU_ADDR(18)
K2, K7
4105 B7
MIU_ADDR(19) K2, K7
4106 B7
MIU_ADDR(20) K2, K7
MIU_ADDR(21)
K2, K7 4107 B7
MIU_ADDR(22)
K2, K7
4108 F14
MIU_ADDR(23) K2, K7
4109 C7
MIU_ADDR(24) K2, K7
4110 B7
5100 I7
I
5101 F5
5102 F5
5103 C5
7100-1 F8
7100-2 E2
7100-3 F2
7100-4 A12
7100-5 G12
7100-6 H5
7100-7 D12
F_15270_054.eps
7100-8 D7
190505
7103 H3
14