Static Random Access Memory (Sram); Control Head; Controller Audio & Signaling Circuits; General - Motorola M11URD6CB1_N Service Manual

GTX LTR/Privacy Plus 800 MHz Mobile Service Manual
Additional EEPROM is contained in the K1µP (U101).
This EEPROM is used to store radio tuning and align-
ment data. Like the external EEPROM this memory can
be programmed multiple times and will retain the data
when power is removed from the radio.
NOTE
The external EEPROM plus the 640 bytes
of internal EEPROM in the 68HC11K1
comprise the complete codeplug.

Static Random Access Memory (SRAM)

The SRAM (U103) contains temporary radio calcula-
tions or parameters that can change very frequently,
and which are generated and stored by the software
during its normal operation. The information is lost
when the radio is turned off. The device allows an
unlimited number of write cycles. SRAM accesses are
indicated by the EN_CS signal U103-20 (which comes
from U101-28) going low. U103 is commonly referred
to as the external RAM as opposed to the internal RAM
which is the 768 bytes of RAM which is part of the
68HC11K1. Both RAM spaces serve the purpose. How-
ever, the internal RAM is used for the calculated values
which are accessed most often. Capacitor C133 serves
to filter out any AC noise which may ride on +5VDC at
U103.

Control Head

Control Head is available for user interface. The Con-
trol Head contains the internal speaker, the micro-
phone connector, several buttons to operate the radio
and several indicator LEDs to inform the user about
the radio status. Additionally Control Head uses a 3
digit LCD (Liquid Crystal Display) for the channel
number.
When turned on, the On/Off switch turns the voltage
regulators on by pulling ON_OFF_CONTROL to high
and connects the base of Q925(P), Q825(K) to FLT_A+.
This transistor pulls the line ANALOG_3 to low to
inform the µP that the On/Off button is pressed. If the
radio is switched off, the µP will switch it on and vice
versa. All other buttons work the same way. If a button
is pressed, it will connect one of the 3 lines ANALOG_
1,2,3 to a resistive voltage divider connected to +5VDC.
The voltages of the lines are A/D converted inside the
µP and specify the pressed button.
All the back light and indicator LEDs are driven by cur-
rent sources and controlled by the µP via SERIAL
PERIPHERAL INTERFACE (SPI) interface. The LED
status is stored in shift register U941(P). Line LED CE
enables the serial write process via Q941(P), while line
LED CLCK BUF shifts the data of line SPI DATA BUF
into the shift register.
In addition Control Head contains the LCD H931, the
display driver U932 and a transistor Q953 to switch the
June, 2000
display driver on and off. Q953 is controlled by the µP
via shift register U941, The display data of line SPI
DATA BUF is shifted into the display driver by clock
signal LCD CLCK BUF.
Controller Audio & Signaling
Circuits

General

Audio Signalling Filter IC (ASFIC)

The ASFIC (U201) used in the controller has four func-
tions;
• RX/TX audio shaping, i.e. filtering, amplifica-
tion, attenuation
• RX/TX signalling, PL/DPL/HST/LST
• Squelch detection
• Microprocessor clock signal generation (see
Microprocessor Clock Synthesizer Description
Block).
The ASFIC is programmable through the SPI BUS
(U201-E3/F1/F2), normally receiving 21 bytes. This
programming sets up various paths within the ASFIC
to route audio and/or signalling signals through the
appropriate filtering, gain and attenuator blocks. The
ASFIC also has 6 General Control Bits GCB0-5 which
are CMOS level outputs. They are used for AUDIO
_PA _ENABLE (GCB0) to switch the audio PA on and
off, EXTERNAL_ALARM (GCB1) to toggle the
EXTERNAL_ALARM pin on the accessory connector
J400-4, B+_CONTROL (GCB2) to switch the voltage
regulators (and the radio) on and FAST_OFF_IGN
(GCB5) which forces the radio-on latch to the off condi-
tion. Two remaining ports, GCB3 and GCB4, are not
used.

Audio Ground

VAG is the dc bias used as an audio ground for the op-
amps that are external to the Audio Signalling Filter IC
(ASFIC). U251 forms this bias by dividing 9V3Vwith
resistors R251, R252, and buffering the 4.65 VDC result
with a voltage follower. VAG emerges at pin 1 of U251.
C235 is a bypass capacitor for VAG. The ASFIC gener-
ates its own 2.5V bias for its internal circuitry. C221 is
the bypass for the ASFIC's audio ground dc bias.
While there are ASFIC VAG, and BOARD
VAG (U201-1), each of these are sepa-
rated. They are not connected together.
6880905Z99-O
Theory of Operation
Controller Audio & Signaling Circuits
NOTE
8-9