Static Random Access Memory (Sram); Control Head Model P - Motorola GTX/LCS 2000 Service Manual

Static Random Access
Memory (SRAM)

Control Head Model P+

access signals (SI, SO and SCK) are generated by the K1µP and chip select (CS)
is generated by address decoder U0105.
Additional EEPROM is contained in the K1µP (U0101). This EEPROM is used
to store radio tuning and alignment data. Like the external EEPROM this memory
can be programmed multiple times and will retain the data when power is removed
from the radio.
Note: The external EEPROM plus the 640 bytes of internal EEP-
ROM in the 68HC11K1 comprise the complete codeplug.
The SRAM (U0103) contains temporary radio calculations or parameters that can
change very frequently, and which are generated and stored by the software during
its normal operation. The information is lost when the radio is turned off. The
device allows an unlimited number of write cycles. SRAM accesses are indicated
by the CS signal U103-20 (which comes from U101-CSGP2) going low. U0103
is commonly referred to as the external RAM as opposed to the internal RAM
which is the 768 bytes of RAM which is part of the 68HC11K1. Both RAM spaces
serve the purpose. However, the internal RAM is used for the calculated values
which are accessed most often. Capacitor C0133 serves to filter out any AC noise
which may ride on +5V at U0103.
Control Head Model P+ is available for user interface. The Control Head contains
the internal speaker, the microphone connector, several buttons to operate the
radio and several indicator LEDs to inform the user about the radio status.
Additionally Control Head P+ uses a 3 digit LCD display for the channel number.
When turned on, the On/Off switch switches the voltage regulators on by pulling
ON OFF CONTROL to high and connects the base of Q0925(P), Q0825(K) to
FLT A+. This transistor pulls the line ANALOG 3 to low to inform the µP that the
On/Off button is pressed. If the radio is switched off, the µP will switch it on and
vice versa. All other buttons work the same way. If a button is pressed, it will
connect one of the 3 lines ANALOG 1,2,3 to a resistive voltage divider connected
to +5V. The voltages of the lines are A/D converted inside the µP and specify the
pressed button.
All the back light and indicator LEDs are driven by current sources and controlled
by the µP via SERIAL PERIPHERAL INTERFACE (SPI) interface. The LED
status is stored in shift register U0941(P). Line LED CE enables the serial write
process via Q0941(P), while line LED CLCK BUF shifts the data of line SPI
DATA BUF into the shift register.
In addition Control Head P contains the LCD display H0931, the display driver
U0932 and a transistor (U0931) to switch the display driver on and off in
emergency condition. Q0931 is controlled by the µP via shift register U0941, The
display data of line SPI DATA BUF is shifted into the display driver by clock
signal LCD CLCK BUF.
Theory of Operation 7-13