Ignition; Hook; Microprocessor Clock Synthesizer; Serial Peripheral Interface (Spi) - Motorola M11URD6CB1_N Service Manual

GTX LTR/Privacy Plus 800 MHz Mobile Service Manual

Ignition

Ignition sense is used to prevent the radio from drain-
ing the vehicle's battery while the engine is not run-
ning.
When the IGNITION input goes above 1.3VDC, Q450,
Q612 and Q611 turn on, supplying SW_B+ to the radio
and enabling U601 and U631 to supply the regulated
voltage (+5 VDC and 9.3 VDC) to all the circuitry. The
µ P s t a r t s t o ru n t h e s o f t w a re , re a d s t h e l i n e
IGNITION_SENSE, determines from the level that the
IGNITION input is active and sets the B+_CONTROL
(via the ASFIC-GCB2) to high and latches SW_B+ on.
When the IGNITION line drops below 1.3 VDC, Q450
switches off and R441 pulls line IGNITION_SENSE
h i g h . T h e s o f t w a r e
IGNITION_SENSE to switch off the radio by setting B+
CONTROL line to low. Whenever the IGNITION line
goes above 1.3 VDC, the above process will be
repeated—depending if the radio was previously on or
off.
The ignition sense capability can be disabled by turn-
ing switch S401-2 & 4 on. This supplies FLT_A+ via
R452 to the ignition sense pin continuously. The radio
is shipped with ignition sense disabled.

Hook

The HOOK line is used to inform the µP when the
Microphone´s hang-up switch is engaged. Depending
on the radio programming the µP turns the audio PA
on or off. The signal is routed from J101-3 and J400-14
through transistor Q101 to the K1µP U101-23. The volt-
age range of HOOK in normal operating mode is 0-5
VDC.

Microprocessor Clock Synthesizer

The clock source for the controller's microprocessor
system is generated by the ASFIC (U201). Upon power-
up the synthesizer (U5701) generates a 2.1 MHz wave-
form that is routed from the RF section (via C202) to the
ASFIC (on U201 XTAL_IN). For the main board con-
troller, the ASFIC uses 2.1 MHz as a reference input
clock signal for its internal synthesizer. The ASFIC, in
addition to audio circuitry, has a programmable syn-
thesizer which can generate a synthesized signal rang-
ing from 1200 Hz to 32.769 MHz with steps of 1200 Hz.
While the radio is turned on, the ASFIC generates a
default 3.6864 MHz CMOS square wave µP CLK (on
U201-UPCLK) which is routed to the µP (U101-
EXTAL). After the µP starts operation, it reprograms
the ASFIC synthesizer clock to a higher µP CLK fre-
quency (usually 7.3728 or 14.7456 MHz) and continues
operation.
The ASFIC synthesizer clock is controlled by the soft-
ware, and may slightly be changed while harmonics of
June, 2000
i s a l e r t e d b y l i n e
6880905Z99-O
Controller Detailed Functional Description
this clock source interfere with the specific radio
receive frequency.
The ASFIC synthesizer loop components (C228, C229
and R222) set the switching time and jitter of the clock
output. If the synthesizer cannot generate the required
clock frequency it will switch back to its default
3.6864 MHz frequency.

Serial Peripheral Interface (SPI)

The µP communicates with the other programmable
ICs through its SPI port. This port consists of SPI
TRANSMIT DATA U101-1, SPI RECEIVE DATA U101-
80, SPI CLK U101-2 and chip select lines going to the
various programmable ICs. This BUS is a synchronous
bus (the timing clock signal CLK is sent with SPI
TRANSMIT DATA or SPI RECEIVE DATA).
In the controller section, there are three ICs on the SPI
BUS: ASFIC (U201-E3), EEPROM (U104-1) and D/A
(U731-6). In the RF sections, there are 2 ICs on the SPI
BUS: Pendulum (Reference Oscillator U5702-24) and
Synthesizer (U5701-7). The SPI TRANSMIT DATA and
CLK lines going to the RF section are filtered with L131
and L132 to minimize noise. The chip select lines for
the ICs are decoded by the address decoder U105.
The SPI BUS is also used for the control head. U106
buffers the SPI TRANSMIT DATA and CLK lines to the
control head. U106 serves also to switch off the CLK
signal for the LCD display while it is not selected via
LCD_CE signal.
When the µP needs to program any of these ICs, it
drops down the chip select line of the specific IC to a
logic 0 and then sends the proper data and clock sig-
nals. The data sent to the various ICs are different. For
example the ASFIC receives 21 bytes (168 bits) while
the DAC needs 3 bytes (24 bits). After the data has been
sent the chip select line is returned to a logic 1.

SBEP Serial Interface

The SBEP serial interface line allows the radio to com-
municate with the Dealer Programming Software
(DPS). This interface connects to the Microphone con-
nector (J902) via Control Head connector (J101) and
comprises BUS+ (J101-15). The line is bi-directional,
meaning that either the radio or the DPS can drive the
line.
The connection from the Control Head is made
through the BUS+ line, via L421 (SCI_RSS line) and
diode CR151 to the U101-78-RxD and U101-79-TxD
ports.

Microprocessor (Open Controller)

For this radio, the K1µP is configured to operate in the
expanded or bootstrap modes. In expanded mode the
K1µP uses external memory ICs, whereas in bootstrap
Theory of Operation
8-7