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Altera JESD204B User Manual

Altera JESD204B User Manual

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JESD204B IP Core User Guide
Last updated for Quartus Prime Design Suite: 16.1
UG-01142
101 Innovation Drive
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2016.10.31
San Jose, CA 95134
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  • Page 1 JESD204B IP Core User Guide Last updated for Quartus Prime Design Suite: 16.1 UG-01142 101 Innovation Drive Subscribe 2016.10.31 San Jose, CA 95134 Send Feedback www.altera.com...

  • Page 2: Table Of Contents

    IP Catalog and Parameter Editor....................... 3-6 Design Walkthrough............................3-7 Creating a New Quartus Prime Project..................3-8 Parameterizing and Generating the IP Core................3-8 Compiling the JESD204B IP Core Design..................3-9 Programming an FPGA Device....................3-10 JESD204B IP Core Design Considerations.....................3-10 Integrating the JESD204B IP core in Qsys..................3-10 Pin Assignments..........................3-11...
  • Page 3 Signals................................4-31 Transmitter............................4-31 Receiver............................4-40 Registers..............................4-48 Register Access Type Convention....................4-48 JESD204B IP Core Deterministic Latency Implementation Guidelines... 5-1 Constraining Incoming SYSREF Signal....................5-1 Programmable RBD Offset......................... 5-2 Programmable LMFC Offset........................5-5 Maintaining Deterministic Latency during Link Reinitialization............5-10 JESD204B IP Core Debug Guidelines..............6-1 Clocking Scheme............................6-1...

  • Page 4: Jesd204B Ip Core Quick Reference

    Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice.
  • Page 5 • Run-time configuration of parameters L,M, and F • Data rates up to 12.5 gigabits per second (Gbps)—per JESD204B specification • Data rates of up to 15 Gbps—not certified per JESD204B specifi‐ cation (uncharacterized support) • Single or multiple lanes (up to 8 lanes per link) •...
  • Page 6 Design Examples for JESD204B IP Core User Guide • JESD204B IP Core Document Archives • on page 7-1 Provides a list of user guides for previous versions of the JESD204B IP core. JESD204B IP Core Quick Reference Altera Corporation Send Feedback...

  • Page 7: About The Jesd204B Ip Core

    Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice.
  • Page 8 About the JESD204B IP Core 2016.10.31 Figure 2-1: Typical System Application for JESD204B IP Core The JESD204B IP core utilizes the Avalon-ST source and sink interfaces, with unidirectional flow of data, to transmit and receive data on the FPGA fabric interface. FPGA...

  • Page 9: Datapath Modes

    TX path. The JESD204B IP core generates a single link with a single lane and up to a maximum of 8 lanes. If there are two ADC links that need to be synchronized, you have to generate two JESD204B IP cores and then manage the deterministic latency and synchronization signals, like SYSREF and SYNC_N, at your custom wrapper level.

  • Page 10: Jesd204B Ip Core Configuration

    For example, if a converter device supports LMF = 442 and LMF = 222, to check the performance for both configurations, you need to generate the JESD204B IP core with maximum F and L, which is L = 4 and F = 2.

  • Page 11: Channel Bonding

    F parameter according to the JESD204B IP Specification for a correct data mapping. To support the High Density (HD) data format, the JESD204B IP core tracks the start of frame and end of frame because F can be either an odd or even number. The start of frame and start of multi-frame wrap around the 32-bits data width architecture.

  • Page 12: Performance And Resource Utilization

    ×N Related Information Arria 10 Device Datasheet • • Arria 10 Transceiver PHY User Guide Performance and Resource Utilization Table 2-4: JESD204B IP Core FPGA Performance Data Rate PMA Speed FPGA Fabric Link Clock F Device Family Enable Hard PCS...
  • Page 13 2.0 to 8.5 2.0 to 8.5 212.50 The following table lists the resources and expected performance of the JESD204B IP core. These results are obtained using the Quartus Prime software targeting the following Altera FPGA devices: • Cyclone V : 5CGTFD9E5F31I7 •...
  • Page 14 The numbers of ALMs and logic registers in this table are rounded up to the nearest 10. Note: The resource utilization data are extracted from a full design which includes the Altera Transceiver PHY Reset Controller IP Core. Thus, the actual resource utilization for the JESD204B IP core should be smaller by about 15 ALMs and 20 registers.
  • Page 15 M10K for Arria V device, M20K for Arria V GZ, Stratix V and Arria 10 devices. The Quartus Prime software may auto-​fit to use MLAB when the memory size is too small. Conversion from MLAB to M20K or M10K was performed for the numbers listed above. About the JESD204B IP Core Altera Corporation Send Feedback...
  • Page 16 M10K for Arria V device, M20K for Arria V GZ, Stratix V and Arria 10 devices. The Quartus Prime software may auto-​fit to use MLAB when the memory size is too small. Conversion from MLAB to M20K or M10K was performed for the numbers listed above. About the JESD204B IP Core Altera Corporation Send Feedback...

  • Page 17: Getting Started

    IP cores in the Quartus Prime software. Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice.

  • Page 18: Installing And Licensing Ip Cores

    The OpenCore ® feature allows evaluation of any Altera FPGA IP core in simulation and compilation in the Quartus Prime software. Upon satisfaction with functionality and performance, visit the Self Service Licensing Center to obtain a license number for any Altera FPGA product.

  • Page 19: Opencore Plus Ip Evaluation

    The Project Navigator displays a banner indicating the IP upgrade status. Click Launch IP Upgrade Tool or Project > Upgrade IP Components to upgrade outdated IP cores. Getting Started Altera Corporation Send Feedback...
  • Page 20 Refer to the Description for details about IP core version differences. If you do not upgrade the IP, the IP variation synthesis and simulation files remain unchanged, and you cannot modify parameters until upgrading. Getting Started Altera Corporation Send Feedback...
  • Page 21 2. To upgrade one or more IP cores that support automatic upgrade, ensure that you turn on the Auto Upgrade option for the IP core(s), and click Perform Automatic Upgrade. The Status and Version columns update when upgrade is complete. Example designs provided with any Altera FPGA IP core regenerate automatically whenever you upgrade an IP core.

  • Page 22: Ip Catalog And Parameter Editor

    Generates/Updates Combined Simulation Setup Script for all Project IP Note: IP cores older than Quartus Prime software version 12.0 do not support upgrade. Altera verifies that the current version of the Quartus Prime software compiles the previous two versions of each IP core.

  • Page 23: Design Walkthrough

    Design Walkthrough This walkthrough explains how to create a JESD204B IP core design using Qsys in the Quartus Prime software. After you generate a custom variation of the JESD204B IP core, you can incorporate it into your overall project. Getting Started...

  • Page 24: Creating A New Quartus Prime Project

    • Enable Altera Debug Master Endpoint • Enable Capability Registers To include existing files, you must specify the directory path to where you installed the JESD204B IP core. (10) You must also add the user libraries if you installed the MegaCore IP Library in a different directory from where you installed the Quartus Prime software.

  • Page 25: Compiling The Jesd204B Ip Core Design

    • IP core design example for simulation—refer to Generating and Simulating the Design Example section in the Design Examples for JESD204B IP Core User Guide. • IP core design example for synthesis—refer to Compiling the JESD204B IP Core Design Example section in the Design Examples for JESD204B IP Core User Guide.

  • Page 26: Programming An Fpga Device

    Related Information Device Programming JESD204B IP Core Design Considerations You must be aware of the following conditions when integrating the JESD204B IP core in your design: • Intergrating the IP core in Qsys • Pin assignments • Adding external transceiver PLL •...

  • Page 27: Pin Assignments

    You can create virtual pins to avoid making specific pin assignments for top-level signals. This is useful when you want to perform compilation, but are not ready to map the design to hardware. Altera recommends that you create virtual pins for all unused top-level signals to improve timing closure.

  • Page 28: Adding External Transceiver Pll

    ) that specifies the timing constraints for the input clocks to your IP core. .sdc When you generate the JESD204B IP core, your design is not yet complete and the JESD204B IP core is not yet connected in the design. The final clock names and paths are not yet known. Therefore, the...
  • Page 29 • Specify the PLL clock reference pin frequency using the command. create_clock • Derive the PLL generated output clocks from the Altera PLL IP Core (for Arria V, Cyclone V and Stratix V) or Altera I/O PLL IP Core (for Arria 10) using the command.
  • Page 30 The table below shows an example where the in this design is an input into the transceiver device_clk pin. The IP core's Avalon-MM interface shares the same clock source as the transceiver refclk management clock. (12) For Arria 10 device only. Getting Started Altera Corporation Send Feedback...

  • Page 31: Jesd204B Ip Core Parameters

    \ mgmt_clk -group {mgmt_clk \ <base and generated clock names as reported by report_clock commands> \ JESD204B IP Core Parameters Table 3-5: JESD204B IP Core Parameters Parameter Value Description Main Tab Device Family Select the targeted device family.
  • Page 32 • TX—instantiates the transmitter to interface to the DAC. • Duplex—instantiates the receiver and transmitter to interface to both the ADC and DAC. JESD204B Subclass • 0 Select the JESD204B subclass modes. • 1 • 0—Set subclass 0 • 2 • 1—Set subclass 1 •...
  • Page 33 This parameter is valid only for Arria 10 devices and when you turn on the Enable Transceiver Dynamic Reconfiguration parameter. (15) To perform dynamic reconfiguration, you have to instantiate the Transceiver Reconfiguration Controller from the IP Catalog and connect it to the JESD204B IP core through the reconfig_to_xcvr interface. reconfig_from_xcvr (16) To support the Transceiver Toolkit in your design, you must turn on this option.
  • Page 34 UG-01142 3-18 JESD204B IP Core Parameters 2016.10.31 Parameter Value Description Enable Capability On, Off Turn on this option to enable capability registers, which Registers (16) provides high level information about the transceiver channel's configuration. Set user-​defined IP 0–255 Set a user-​defined numeric identifier that can be read from the...
  • Page 35 UG-01142 3-19 JESD204B IP Core Parameters 2016.10.31 Transmitted bits per 1–32 Set the number of transmitted bits per sample (JESD204 sample (N') word size, which is in nibble group). Note: If parameter CF equals to 0 (no control word), parameter N' must be larger than or equal to sum of parameter N and parameter CS (N' ≥...

  • Page 36: Jesd204B Ip Core Component Files

    Contains IP core library mapping information required by the Quartus Prime software.The Quartus Prime software generates a . sip file during generation of some Altera IP cores. You must add any generated .sip file to your project for use by NativeLink simulation and the Quartus Prime Archiver.

  • Page 37: Jesd204B Ip Core Testbench

    PHY Reset Controller IP core. Some configurations are preset and are not programmable in the JESD204B IP core testbench. For example, the JESD204B IP core always instantiates in duplex mode even if RX or TX mode is selected in the JESD204B parameter editor.

  • Page 38: Generating And Simulating The Ip Core Testbench

    2016.10.31 Generating and Simulating the IP Core Testbench You can simulate your JESD204B IP core variation by using the provided IP core demonstration testbench. To use the JESD204B IP core testbench, follow these steps: 1. Generate the simulation model. Refer to Generating the Testbench Simulation Model on page 3-22.
  • Page 39 <example_design_directory> run_altera_jesd204_tb.sh /ip_sim/testbench/ cadence To simulate the testbench design using the ModelSim-Altera or Aldec Riviera-PRO simulator, follow these steps: 1. Launch the ModelSim-Altera or Aldec Riviera-PRO simulator. 2. On the File menu, click Change Directory > Select <example_design_directory>/ip_sim/testbench/ <simulator name>.

  • Page 40: Testbench Simulation Flow

    Transceiver Reset Controller IP to assert. 3. The reset signal of the JESD204B TX Avalon-MM interface is released (go HIGH) once the tx_ready signal is asserted. At the next positive edge of the signal, the JESD204B TX link powers up by link_clk releasing its reset signal.

  • Page 41: Jesd204B Ip Core Functional Description

    Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice.
  • Page 42 UG-01142 JESD204B IP Core Functional Description 2016.10.31 Figure 4-1: Overview of the JESD204B IP Core Block Diagram Transport Layer Data Link Layer Physical Layer JESD204B JESD204B IP Core Design Example jesd204_tx_top DAC Application MAC (jesd204_tx_base) PHY (jesd204_tx_phy) SYNC~ Layer Driver...
  • Page 43 JESD204B TX and RX Transport Layer with Base and Transceiver (Design Example) 32-Bits Architecture The JESD204B IP core consist of 32-bit internal datapath per lane. This means that JESD204B IP Core expects the data samples to be assembled into 32-bit data (4 octets) per lane in the transport layer before sending the data to the Avalon-ST data bus.

  • Page 44: Transmitter

    You are recommended to release the reset for the CSR configuration rxframe_clk space first. All run-time JESD204B configurations like L, F, M, N, N', CS, CF, and HD should be set before releasing the reset for link and frame clock domain.

  • Page 45: Tx Data Link Layer

    Alignment Sequence (ILAS), performs scrambling, lane insertion and frame alignment of characters. TX Data Link Layer The JESD204B IP core TX data link layer includes three phases to establish a synchronized link—Code Group Synchronization (CGS), Initial Lane Synchronization (ILAS), and User Data phase.
  • Page 46 S = Number of samples per converter per frame CF[4:0] HD = High Density data format CF = Number of control words per frame clock per link (18) Applies to Subclass 2 only. JESD204B IP Core Functional Description Altera Corporation Send Feedback...
  • Page 47 SYNC_N will stay in ILAS phase indefinitely until this setting changes. • Link reinitialization through CSR is initiated. The JESD204B IP core transmits /K/ character and causes the RX converter to enter CGS phase. After RX deasserts , the CSR enters ILAS phase and will SYNC_N stay in that phase indefinitely until this setting changes.

  • Page 48: Tx Phy Layer

    2016.10.31 Character replacement for scrambled data The character replacement for scrambled data in the IP core follows these JESD204B specification rules: • At end of frame (not coinciding with end of multi-frame), which equals to 0xFC (D28.7), the transmitter encodes the octet as /F/ character (K28.7).

  • Page 49: Rx Data Link Layer

    RX Data Link Layer The JESD204B IP core RX data link layer buffers incoming user data on all lanes until the RX elastic buffers can be released. Special character substitution are done in the TX link so that the RX link can execute frame and lane alignment monitoring based on the JESD204B specification.
  • Page 50 16 octets to recover the end-of-frame pointer for character replacement. When is set to 1 (default JESD204B setting), the number of octets to be discarded csr_lane_sync_en depends on the scrambler or descrambler block. The receiver assumes that a new frame starts in every F octets. The octet counter is used for frame alignment and lane alignment.
  • Page 51 LMFC boundary. If you want to implement an early release mechanism, program it in the register. The is a counter based on the link clock csr_rbd_offset csr_rbd_offset csr_rbd_count boundary (not frame clock boundary). Therefore, the RBD release opportunity is at every four octets. JESD204B IP Core Functional Description Altera Corporation Send Feedback...

  • Page 52: Rx Phy Layer

    The 8B/10B decoder decode the data after receiving the data through the serial line. The JESD204 IP core supports transmission order from MSB first as well as LSB first. The PHY layer can detect 8B/10B not-in-table (NIT) error and also running disparity error. JESD204B IP Core Functional Description Altera Corporation Send Feedback...

  • Page 53: Operation

    2016.10.31 Operation Operating Modes The JESD204B IP core supports Subclass 0, 1, and 2 operating modes. Subclass 0 The JESD204 IP core maintains a LMFC counter that counts from 0 to (F × K/4)–1 and wraps around again. The LMFC counter starts counting at the deassertion of SYNC_N signal from multiple DACs after synchronization.

  • Page 54: Scrambler/Descrambler

    In some applications, multiple converters are grouped together in the same group path to sample a signal (referred as multipoint link). The FPGA can only start the LMFC counter and its transition to ILAS after all the links deassert the synchronization request. The JESD204B TX IP core provides three signals to facilitate this application. The is the direct signal from the DAC converters.

  • Page 55: Sync_N Signal

    SYNC* (1) Note: 1. SYNC* is not associated to SYNC_N in the JESD204B specification. SYNC* refers to JESD204A (Subclass 0) converter devices that may support synchronization via additional SYNC signalling. For Subclass 1 implementation, you may choose to combine or not to combine the...

  • Page 56: Link Reinitialization

    DAC Reference Clock FPGA Reference Clock Clock Chip SYSREF SYSREF and SYSREF Related Information Programmable RBD Offset on page 5-2 Link Reinitialization The JESD204B TX and RX IP core support link reinitialization. JESD204B IP Core Functional Description Altera Corporation Send Feedback...

  • Page 57: Link Startup Sequence

    SYNC_N device enables the JESD204B TX IP core to exit CGS phase. The IP core ensures that at least one SYSREF rising edge is sampled before exiting CGS phase and entering ILAS phase. This is to prevent a race condition where the is deasserted before SYSREF is sampled.

  • Page 58: Error Reporting Through Sync_N Signal

    LMFC count instead of the updated LMFC count after SYSREF is sampled. RX (Subclass 2) The JESD204B RX IP core behaves the same as in Subclass 1 mode. In this mode, the logic device is always the master timing reference. Upon...
  • Page 59 2016.10.31 Clock Signal Formula Description Data rate/40 The timing reference for the JESD204B IP core.The TX/RX Link Clock: link clock runs at data rate/40 because the IP core operates in a 32-bit data bus architecture after 8B/ txlink_clk 10B encoding.
  • Page 60 The parallel clock is for the transmitter PMA and PCS within the PHY. This clock is internal to the transceiver and is not exposed in the JESD204B IP core. For Arria V, Cyclone V, and Stratix V devices, these...

  • Page 61: Device Clock

    You need to utilize the Altera PLL IP core (in Arria V and Stratix V devices) or Altera IOPLL IP core (in Arria 10 devices) to generate the link clock and frame clock. The link clock is used in the JESD204 IP core (MAC) and the transport layer.
  • Page 62 The phase offset between the SYSREF to the FPGA and converter devices should be minimal. 2. For Arria 10 devices, the transceiver PLL is outside of the JESD204B IP core. For Arria V, Cyclone V, and Stratix V devices, the transceiver PLL is part of the JESD204B IP core.

  • Page 63: Link Clock

    The phase offset between the SYSREF to the FPGA and converter devices should be minimal. 2. For Arria 10 devices, the transceiver PLL is outside of the JESD204B IP core. For Arria V, Cyclone V, and Stratix V devices, the transceiver PLL is part of the JESD204B IP core.

  • Page 64: Local Multi-Frame Clock

    SYSREF. Therefore, you can generate both the link clock and frame clock using direct mode in the Altera PLL IP core. If F = 4, where link clock is the same as...

  • Page 65: Clock Correlation

    The link clock and frame clock are running at the same frequency. You only need to generate one clock from the Altera PLL or Altera IO PLL IP core. In this example, the frame clock may not be able to run up to 1 GHz in the FPGA fabric. The JESD204B (22) transport layer in the design example supports running the data stream of half rate (1 GHz/2 = 500 MHz), at two times the data bus width or of quarter rate (1GHz/4 = 250 MHz), at four times the data bus width.

  • Page 66: Reset Scheme

    • on page 4-24 Reset Scheme All resets in the JESD204B IP core are synchronous reset signals and should be asserted and deasserted synchronously. Note: Ensure that the resets are synchronized to the respective clocks for reset assertion and deassertion.

  • Page 67: Reset Sequence

    Altera recommends that you assert reset for the JESD204B IP core and transport layer when powering up the PLLs and transceiver. Refer to the Altera Transceiver PHY IP Core User Guide and Altera Arria 10 Transceiver PHY IP Core User (23)

  • Page 68: Adc-Fpga Subsystem Reset Sequence

    • For Stratix V, Arria V, and Cyclone V devices, this is the clock for the transceiver reconfiguration controller. b. The second reference clock is the device clock to the core PLL (Altera I/O PLL for Arria 10 devices and Altera PLL for Stratix V, Arria V, and Cyclone V devices).
  • Page 69 Controller is asserted), deassert the Avalon-MM interface reset for the IP core. At the configuration phase, the subsystem can program the JESD204B IP core if the default IP core register settings need to change. 7. Deassert both the link reset for the IP core and the frame reset for the transport layer.

  • Page 70: Fpga-Dac Subsystem Reset Sequence

    • For Stratix V, Arria V, and Cyclone V devices, this is the clock for the transceiver reconfiguration controller. b. The second reference clock is the device clock to the core PLL (Altera I/O PLL for Arria 10 devices and Altera PLL for Stratix V, Arria V, and Cyclone V devices).

  • Page 71: Signals

    Transceiver PHY Reset Controller is asserted), deassert the Avalon-MM interface reset for the IP core. At the configuration phase, the subsystem can program the JESD204B IP core if the default IP core register settings need to change. 7. Deassert both the link reset for the IP core and the frame reset for the transport layer.
  • Page 72 TX calibration in progress signal. This signal is tx_cal_busy[] asserted to indicate that the TX transceiver calibration is in progress. (24) The Transceiver PHY Reset Controller IP Core controls this signal. JESD204B IP Core Functional Description Altera Corporation Send Feedback...
  • Page 73 Transceiver Reconfiguration Controller IP core regardless of whether run-time reconfigura‐ tion is enabled or disabled. The Transceiver Reconfiguration Controller IP core also supports various calibration function during transceiver power up. JESD204B IP Core Functional Description Altera Corporation Send Feedback...
  • Page 74 This signal is only available if you enable dynamic reconfiguration for Arria 10 FPGA variants. The output data. Output reconfig_avmm_ readdata[] This signal is only available if you enable dynamic reconfiguration for Arria 10 FPGA variants. JESD204B IP Core Functional Description Altera Corporation Send Feedback...
  • Page 75 Indicates that the Avalon-ST sink interface in jesd204_tx_link_ the TX core is ready to accept data. The ready Avalon-ST sink interface asserts this signal on the JESD204B link state of USER_DATA phase. The ready latency is 0. JESD204B IP Core Functional Description Altera Corporation Send Feedback...
  • Page 76 The Avalon-MM interface clock signal. This jesd204_tx_avs_clk clock is asynchronous to all the functional clocks in the JESD204B IP core. The JESD204B IP core can handle any cross clock ratio and therefore the clock frequency can range from 75 MHz to 125 MHz.
  • Page 77 This signal is asserted by the Avalon-MM slave jesd204_tx_avs_ to indicate that it is unable to respond to a read waitrequest or write request. The JESD204B IP core ties this signal to 0 to return the data in the access cycle. Signal...
  • Page 78 Input Indicates a multidevice synchronization mdev_sync_n request. Synchronize signal combination should be done externally and then input to the JESD204B IP core through this signal. • For subclass 0—combine the dev_sync_n signal from all multipoint links before connecting to the signal.
  • Page 79 Output Indicates the address space that is reserved for csr_tx_testmode[] DLL testing within the JESD204B IP core. • 0—reserved for the IP core. • 1—program different tests in the transport layer. Refer to register.

  • Page 80: Receiver

    Signal Width Direction Description Out-of-band (OOB) Output Interrupt pin for the JESD204B IP core. jesd204_tx_int Interrupt is asserted when any error or synchronization request is detected. Configure register to set the type of tx_err_enable error that can trigger an interrupt.
  • Page 81 Recovered clock signal. This clock is derived from rxphy_clk[] the clock data recovery (CDR) and the frequency depends on the JESD204B IP core data rate. For PCS option in Hard PCS or Soft PCS mode, this clock has the same frequency as the rxlink_ signal.
  • Page 82 This signal is only available if you enable dynamic reconfiguration for Arria 10 FPGA variants. The input data. Input reconfig_avmm_ writedata[] This signal is only available if you enable dynamic reconfiguration for Arria 10 FPGA variants. JESD204B IP Core Functional Description Altera Corporation Send Feedback...
  • Page 83 Indicates an empty data stream due to invalid data. jesd204_rx_frame_error This signal is asserted high to indicate an error during data transfer from the RX core to the transport layer. Signal Width Direction Description Avalon-MM Interface JESD204B IP Core Functional Description Altera Corporation Send Feedback...
  • Page 84 The Avalon-MM interface clock signal. This clock jesd204_rx_avs_clk is asynchronous to all the functional clocks in the JESD204B IP core. The JESD204B IP core can handle any cross clock ratio and therefore the clock frequency can range from 75 MHz to 125 MHz.
  • Page 85 This signal is asserted by the Avalon-MM slave to jesd204_rx_avs_ indicate that it is unable to respond to a read or waitrequest write request. The JESD204B IP core ties this signal to 0 to return the data in the access cycle. Signal Width...
  • Page 86 The transport layer can use this signal as a run-time parameter. Output Indicates the high density data format. The csr_hd transport layer can use this signal as a run-time parameter. JESD204B IP Core Functional Description Altera Corporation Send Feedback...
  • Page 87 Signal Width Direction Description Out-of-band (OOB) Output Interrupt pin for the JESD204B IP core. Interrupt is jesd204_rx_int asserted when any error is detected. Configure the register to set the type of error that rx_err_enable can trigger an interrupt. Signal...

  • Page 88: Registers

    4-48 Registers 2016.10.31 Registers The JESD204B IP core supports a basic one clock cycle transaction bus. There is no support for burst mode and wait-state feature (the signal is tied to 0). The JESD204B IP core Avalon-MM slave avs_waitrequest interface has a data width of 32 bits and is implemented based on word addressing. The Avalon-MM slave interface does not support byte enable access.
  • Page 89 • Software writes 1 shall set the bit to 1. • Hardware clears the bit to 0, if the bit has been set to 1 by software. • Software set has higher priority than hardware clear. JESD204B IP Core Functional Description Altera Corporation Send Feedback...

  • Page 90: Jesd204B Ip Core Deterministic Latency Implementation Guidelines

    Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice.

  • Page 91: Programmable Rbd Offset

    Record the value. rx_status0 2. Power cycle the JESD204B subsystem, which consists of the FPGA and converter devices. 3. Read the RBD count again and record the value. 4. Repeat steps 1 to 3 at least 5 times and record the RBD count values.
  • Page 92 1 link clock or LMFC count to cater for power cycle variation Aligned outputs on all lanes RBD Elastic Buffers Released Set csr_rbd_offset = 1 JESD204B IP Core Deterministic Latency Implementation Guidelines Altera Corporation Send Feedback...
  • Page 93 RBD offset is one of the techniques to overcome this issue. Not every RBD offset value is legal. Figure below illustrates the technique to decide the legal RBD offset value. JESD204B IP Core Deterministic Latency Implementation Guidelines Altera Corporation...

  • Page 94: Programmable Lmfc Offset

    4-14 Programmable LMFC Offset If your JESD204B subsystem design has deterministic latency issue, the programmable LMFC offset in the TX and RX IP cores provides flexibility to ensure that deterministic latency can be achieved. The TX LMFC offset can align the TX LMFC counter to the LMFC counter in DAC; the RX LMFC offset can align the RX LMFC counter to the LMFC counter in ADC.
  • Page 95 5. The LMFC phase offset between the LMFC counter at ADC and FPGA is ~3.5 link clock cycles. 6. The FPGA deasserts SYNC_N at the LMFC boundary. 7. The ADC JESD204B core detects the SYNC_N deassertion. 8. Because SYNC_N deassertion is detected after the second LMFC boundary at ADC, ILAS transmission begins at the third LMFC boundary.
  • Page 96 Latest arrival lane in multiple power cycles You can use the TX LMFC offset to align the LMFC counter in IP core to the LMFC counter in DAC. JESD204B IP Core Deterministic Latency Implementation Guidelines Altera Corporation Send Feedback...
  • Page 97 5. The LMFC phase offset is ~3.5 link clock cycles. 6. The DAC deasserts SYNC_N at the LMFC boundary. 7. SYNC_N deassertion is detected by the JESD204B IP core. 8. Because SYNC_N deassertion is detected after the second LMFC boundary at the FPGA, ILAS transmission begins at the third LMFC boundary.
  • Page 98 5. The LMFC boundary is delayed by 4 link clock. 6. The DAC deasserts SYNC_N at the LMFC boundary. 7. SYNC_N deassertion is detected by the JESD204B IP core. 8. Because LMFC boundary is delayed by 4 link clock, the IP core detects the SYNC_N deassertion before the second LMFC boundary.

  • Page 99: Maintaining Deterministic Latency During Link Reinitialization

    If you are performing a link reset by asserting to reinitialize the link, set txlink_rst_n rxlink_rst_n bit to "1" to force the IP core to resample the SYSREF pulse without asserting csr_sysref_singledet signal. jesd204_tx_avs_rst_n jesd204_rx_avs_rst_n JESD204B IP Core Deterministic Latency Implementation Guidelines Altera Corporation Send Feedback...

  • Page 100: Jesd204B Ip Core Debug Guidelines

    If you use the MIF to store the SPI register settings of the Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S.

  • Page 101: Converter And Fpga Operating Conditions

    "0", missing or extra bits in a MIF content row. Check these items: • For example, in the ADI AD9250 converter, Altera recommends that you first perform register bit setting for the scramble (SCR) or lane (L) register at address 0x6E before setting the quick configura‐...

  • Page 102: Creating A Signaltap Ii Debug File To Match Your Design Hierarchy

    2016.10.31 Creating a SignalTap II Debug File to Match Your Design Hierarchy The SignalTap II and system console are very useful tools in debugging the JESD204B link related issues. ® The SignalTap II provides a dynamic view of signals. For Arria 10 devices, the Quartus Prime Standard Edition software generates two files, build_stp.tcl...

  • Page 103: Debugging Jesd204B Link Using System Console

    Note: The GUI allows you to choose the appropriate instance for each IP core name if your design contains more than one JESD204B IP instances. For simplex core, you need to choose the RX instance followed by TX instance in order to generate the proper STP file.
  • Page 104 • tx_cal_busy Use the signal as sampling clock for the SignalTap II. rxphy_clk[0] txphy_clk[0] For a normal operation of the JESD204B RX path, the bit for each lane should be rx_is_lockedtodata "1" while the , and bit for each lane should be "0".
  • Page 105 Upon receiving 4 consecutive /K/ characters, the link layer deasserts the signal. rx_dev_sync_n f. The JESD204B link transition from CGS to ILAS phase when ADC transmit /R/ or 1C hexadecimal after /K/ character. g. Start of 2 multi-frame in ILAS phase. 2 multi-frame contains the JESD204B link configuration data.
  • Page 106 Figure 6-2: Ramp Pattern on the jesd204_rx_dataout This is a SignalTap II image during the JESD204B user data phase with ramp pattern transmitted from the ADC. Verify the TX transport layer operation using these signals in the altera_jesd204_transport_tx_top.sv: • txframe_rst_n •...
  • Page 107 UG-01142 Debugging JESD204B Link Using System Console 2016.10.31 the data mapping tables in the TX Path Data Remapping section in Design Examples for JESD204B IP Core User Guide) by referring to the bus. jesd204_tx_datain Related Information • AN 696: Using the JESD204B MegaCore Function in Arria V Devices More information about the performance and interoperability of the JESD204B IP core.

  • Page 108: Jesd204B Ip Core Document Archives

    JESD204B IP Core User Guide Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice.

  • Page 109: Jesd204B Ip Core Document Revision History

    • Updated Channel Bonding description. Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice.
  • Page 110 • Updated the data rate support—uncharacterized support for data rates of up to 15 Gbps. • Updated the data rate for Arria 10 and Arria V GT/ST in the JESD204B IP Core FPGA Performance table. • Updated the JESD204B IP Core FPGA Resource Utilization table.
  • Page 111 • N' value from 4-32 to 1-32 • Updated the JESD204B IP Core FPGA Performance table. • Updated the JESD204B IP Core FPGA Resource Utilization table. • Added new parameters to the JESD204B IP Core Parameters table: • Enable Capability Registers • Set user-defined IP identifier •...
  • Page 112 Version Changes December 2014.12.15 • Updated the JESD204B IP Core FPGA Performance table with the data 2014 rate range. • Updated the JESD204B IP Core FPGA Resource Utilization table. • Updated the JESD204B IP Core Parameters table with the following changes: •...
  • Page 113 • Updated the Performance and Resource utilization values. • Updated the Getting Started chapter to reflect the new IP Catalog and parameter editor. • Added the following new sections to further describe the JESD204B IP core features: • Channel Bonding •...

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