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Altera Arria 10 User Manual

Altera Arria 10 User Manual

Avalon-mm dma interface for pcie solutions
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Arria 10 Avalon-MM DMA Interface for PCIe Solutions
User Guide
Last updated for Quartus Prime Design Suite: 15.1
UG-01145_avmm_dma
101 Innovation Drive
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2015.11.02
San Jose, CA 95134
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Summary of Contents for Altera Arria 10

  • Page 1 Arria 10 Avalon-MM DMA Interface for PCIe Solutions User Guide Last updated for Quartus Prime Design Suite: 15.1 UG-01145_avmm_dma 101 Innovation Drive Subscribe 2015.11.02 San Jose, CA 95134 Send Feedback www.altera.com...
  • Page 2 Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
  • Page 3 63Gbps Related Information • Introduction to Altera IP Cores Provides general information about all Altera IP cores, including parameterizing, generating, upgrading, and simulating IP. Creating Version-Independent IP and Qsys Simulation Scripts • Create simulation scripts that do not require manual updates for software or IP version upgrades.
  • Page 4 Table 1-2: Feature Comparison for all Hard IP for PCI Express IP Cores The table compares the features of the three mainstream Hard IP for PCI Express IP Cores. Refer to the Arria 10 Avalon-ST Interface with SR-IOV PCIe Solutions User Guide for the features of that variant.
  • Page 5 1, 2, 4, 8, 16, or 32 1, 2, 4, 8, 16, or 32 1, 2, 4, 8, 16, or 32 requests MSI-X Supported Supported Supported Legacy interrupts Supported Supported Supported Expansion ROM Supported Not supported Not supported Datasheet Altera Corporation Send Feedback...
  • Page 6 AtomicOp Request FetchAdd The Arria 10 Avalon-MM DMA Interface for PCIe Solutions User Guide explains how to use this IP core and not the PCI Express protocol. Although there is inevitable overlap between these two purposes, use this document only in conjunction with an understanding of the PCI Express Base Specification.
  • Page 7 Altera verifies that the current version of the Quartus Prime software compiles the previous version of each IP core, if this IP core was included in the previous release. Altera reports any exceptions to this verification in the Altera IP Release Notes or clarifies them in the Quartus Prime IP Update tool. Altera does not verify compilation with IP core versions older than the previous release.
  • Page 8 Design Examples 2015.11.02 Related Information • Altera's PCI Express Web Page Design Examples Qsys example designs are available for the Arria 10 Avalon-MM DMA for PCI Express IP Core. You can download them from the directory. <install_dir>/ip/altera/altera_pcie/altera_pcie_a10_ed/example_design/a10 Related Information •...
  • Page 9 Quartus Prime software targeting an Arria 10 device. With the exception of M20K memory blocks, the numbers of ALMs and logic registers are rounded up to the nearest 50.
  • Page 10 1. Select parameters for that variant. 2. For Arria 10 devices, you can use the new Example Design tab of the component GUI to generate a design that you specify. Then, you can simulate this example and also download it to an Arria 10 FPGA Development Kit.
  • Page 11 MSI-X related to PCI Express. Altera Applications engineers regularly update content and add new design examples. These examples help designers like you get more out of the Altera PCI Express IP core and may decrease your time-to-market. The design examples of the Altera Wiki page provide useful guidance for developing your own design.
  • Page 12 Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
  • Page 13 Design Components for the Avalon-MM with DMA Testbench Figure 2-3: Block Diagram for the Qsys DMA Design Example Simulation Testbench PCI Express Example Design Testbench Root Port BFM Arria 10 Hard IP for PCI Express Using Avalon-MM (pcie_example_design_inst) with DMA Application Layer Interface Avalon-MM to...
  • Page 14 On-Chip memory and Host Memory. • A testbench monitor that checks expected results. • The Arria 10 Hard IP for PCI Express Endpoint with the Instantiate internal descriptor controller parameter enabled. The automatically generated testbench performs downstream memory reads and writes. You can edit the...
  • Page 15 Generating the Design 2015.11.02 Figure 2-4: Qsys System Contents for Arria 10 PCI Express DMA Design Example This view of the Arria 10 PCI Express DMA Design Example shows only the Avalon-MM, clock, and reset interfaces. Generating the Design Figure 2-5: Procedure...
  • Page 16 8. For Target Development Kit select the Arria 10 FPGA Development Kit ES2 option. Note: SRAM object file (.sof) generation is only supported for Arria 10 ES2 devices in the 15.1 Quartus Prime release. Arria 10 production devices will be available in a future Quartus Prime release.
  • Page 17 6. apps_type_hwtcl 2. do msim_setup.tcl 3. ld_debug 4. run -all 5. A successful simulation ends with the following message, "Simulation stopped due to successful completion!" Arria 10 PCI Express Quick Start Guide Altera Corporation Send Feedback...
  • Page 18 3. Include the following command in my_setup.sh source ncsim_setup.sh USER_DEFINED_SIM_ OPTIONS="" 4. chmod +x *.sh 5. ./my_setup.sh 6. A successful simulation ends with the following message, "Simulation stopped due to successful completion!" Arria 10 PCI Express Quick Start Guide Altera Corporation Send Feedback...
  • Page 19 UG-01145_avmm_dma Compiling and Simulating the Design 2015.11.02 Figure 2-8: Partial Transcript from Successful Avalon-MM DMA Simulation Testbench Arria 10 PCI Express Quick Start Guide Altera Corporation Send Feedback...
  • Page 20 Hardware. Software. Figure 2-10: Software Application to Test the PCI Express Design Example on the Arria 10 GX FPGA Development Kit A software application running on a Windows PC performs the same hardware test for all of the PCI Express Design Examples.
  • Page 21 Programmer). d. Open the Windows Device Manager and scan for hardware changes. e. Select the Altera FPGA listed as an unknown PCI device and point to the appropriate 32- or 64-bit driver (altera_pice_win_driver.inf) in the Windows_driver directory. f. After the driver loads successfully, a new device named Altera PCI API Device appears in the Windows Device Manager.
  • Page 22 5. The test displays the message, PASSED, if the test is successful. Related Information Arria 10 Development Kit Conduit Interface • on page 6-27 • Arria 10 GX FPGA Development Kit Arria 10 PCI Express Quick Start Guide Altera Corporation Send Feedback...
  • Page 23 Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
  • Page 24 If you plan to replace the Descriptor Controller IP core with your own implementation, do not turn on the Instantiate internal descriptor controller in the parameter editor when parameterizing the IP core. Figure 3-1: Block Diagram of Arria 10 Avalon-MM DMA for PCI Express Qsys System Design Arria 10 Hard IP for PCI Express...
  • Page 25 UG-01145_avmm_dma Generating the Testbench 2015.11.02 Figure 3-2: Arria 10 Avalon-MM DMA for PCI Express Qsys System Design 4. Click Generate > Generate Testbench System. The Generation dialog box appears. 5. Specify the following parameters: Table 3-1: Parameters to Specify in the Generation Dialog Box...
  • Page 26 3. To run the simulation, type the following commands in a terminal window: do msim_setup.tcl ld_debug command compiles all design files and elaborates the top-level design without any ld_debug optimization. run -all The simulation performs the following operations: Getting Started with the Avalon-MM DMA Altera Corporation Send Feedback...
  • Page 27 The PCI Express testbenches run simulations at the register transfer level (RTL). However, it is possible to create your own gate-level simulations. Contact your Altera Sales Representative for instructions and an example that illustrates how to create a gate-level simulation from the RTL testbench.
  • Page 28 In the Family list, select Arria 10 (GX/SX/GT). b. In the Devices list, select All. c. In the Available devices list, select the appropriate device. For Arria 10 ES2 development kits, select 10AX115S1F45I3SGE2. 9. Click Next to close this page and display the EDA Tool Settings page.
  • Page 29 This Qsys design example block diagram shows how to connect the external Descriptor Controller to the Hard IP for PCI Expess with Avalon-MM DMA interface. This design example is available in <install_dir>/ ip/altera/altera_pcie/altera_pcie_hip_256_avmm/example_design/<dev> Figure 3-3: External Descriptor Controller Connectivity Getting Started with the Avalon-MM DMA Altera Corporation Send Feedback...
  • Page 30 Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
  • Page 31 PCIe link. This option is recommended for typical endpoint applications where most of the PCIe Parameter Settings Altera Corporation Send Feedback...
  • Page 32 Each data credit is 20 bytes. Table 4-2: RX Buffer Allocation Selections Available by Interface Type Interface Type Minimum Balanced High Maximum Avalon-ST Available Available Available Available Available Avalon-MM Available Available Available Not Available Not Available Parameter Settings Altera Corporation Send Feedback...
  • Page 33 Available Related Information PCI Express Base Specification 3.0 • • Arria 10 Transceiver PHY User Guide Provides information about the ADME feature for Arria 10 devices. Arria 10 Avalon-MM Settings Table 4-3: Avalon Memory-Mapped System Settings Parameter Value Description Avalon-MM address...
  • Page 34 Turn this option on, if you plan to use the Altera-provided descriptor controller in your design. Turn this option off if you plan to modify or replace the descriptor controller logic in your design.
  • Page 35 Register Name Range Default Value Description Vendor ID 16 bits 0x00001172 Sets the read-only value of the register. This Vendor ID parameter cannot be set to 0xFFFF, per the PCI Express Specification. Address offset: 0x000. Parameter Settings Altera Corporation Send Feedback...
  • Page 36 This group of parameters defines various capability properties of the IP core. Some of these parameters are stored in the PCI Configuration Space - PCI Compatible Configuration Space. The byte offset indicates the parameter address. Parameter Settings Altera Corporation Send Feedback...
  • Page 37 • 0011 Ranges A and B • 0110 Ranges B and C • 0111 Ranges A, B, and C • 1110 Ranges B, C and D • 1111 Ranges A, B, C, and D Parameter Settings Altera Corporation Send Feedback...
  • Page 38 UG-01145_avmm_dma Error Reporting 2015.11.02 Parameter Possible Values Default Value Description All other values are reserved. Altera recommends that the completion timeout mechanism expire in no less than 10 ms. Disable On/Off Disables the completion timeout mechanism. When On, completion the core supports the completion timeout disable...
  • Page 39 MSI messages 1, 2, 4, 8, 16, 32 Specifies the number of messages the Application Layer can requested request. Sets the value of the Multiple Message Capable field of the register, 0x050[31:16]. Message Control Parameter Settings Altera Corporation Send Feedback...
  • Page 40 1. Throughout this user guide, the terms word, dword and qword have the same meaning that they have in the PCI Express Base Specification. A word is 16 bits, a dword is 32 bits, and a qword is 64 bits. Parameter Settings Altera Corporation Send Feedback...
  • Page 41 In combination with the Slot power scale value, specifies the upper 0–255 limit in watts on power supplied by the slot. Refer to Section 7.8.9 of the PCI Express Base Specification for more information. Slot number Specifies the slot number. 0-8191 Parameter Settings Altera Corporation Send Feedback...
  • Page 42 Active State Power Management (ASPM). This setting is disabled for Root Ports. The default value of this parameter is 1 µs. This is the safest setting for most designs. Parameter Settings Altera Corporation Send Feedback...
  • Page 43 Hard IP Reconfiguration Interface. tion of PCIe read-only registers Enable Altera When On, you can use the Altera System Console to read and write On/Off Debug Master the embedded Arria 10 Native PHY registers. Endpoint (ADME)
  • Page 44 Only Verilog HDL is supported. HDL format Target Arria 10 FPGA Select Arria 10 FPGA Development Kit for Arria 10 production Development Development Kit devices. Select Arria 10 FPGA Development Kit ES for engineering sample (ES) or ES2 devices. Select None if you are Arria 10 FPGA targeting your own development board.
  • Page 45 Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
  • Page 46 UG-01145_avmm_dma Physical Layout of Hard IP In Arria 10 Devices 2015.11.02 Figure 5-1: Arria 10 Devices with 96 Transceiver Channels and Four PCIe Hard IP Blocks GT 115 UF45 GXBL1J GXBL1J Transceiver Transceiver Transceiver GXBR4J GXBR4J GT 090 UF45 Bank...
  • Page 47 UG-01145_avmm_dma Physical Layout of Hard IP In Arria 10 Devices 2015.11.02 Figure 5-2: Arria 10 Devices with 72 Transceiver Channels and Four PCIe Hard IP Blocks GT 115 SF45 GXBR4I GXBR4I Transceiver Transceiver Transceiver GXBL1H GXBL1H GT 090 SF45 Bank...
  • Page 48 PCIe Gen1 - Gen3 Hard IP blocks with CvP capabilities PCIe Gen1 - Gen3 Hard IP blocks without CvP capabilities Refer to the Arria 10 Transceiver Layout in the Arria 10 Transceiver PHY User Guide for comprehensive figures for Arria 10 GT, GX, and SX devices.
  • Page 49 For the possible values of <txvr_block_N> and <txvr_block_N+1>, refer to the figures that show the physical location of the Hard IP PCIe blocks in the different types of Arria 10 devices, at the start of this chapter. For each HIP block, the transceiver block that is adjacent and extends below the HIP block, is <txvr_block_N>, and the transceiver block that is directly above <txvr_block_N>...
  • Page 50 Channel Placement and fPLL Usage for the Gen1 and Gen2 Data Rates The following figures illustrate the x1, x2, x4, and x8 channel placement for the Arria 10 Hard IP for PCI Express. In these figures, channels that are not used for the PCI Express protocol are available for other protocols.
  • Page 51 UG-01145_avmm_dma Channel Placement and fPLL Usage for the Gen1 and Gen2 Data Rates 2015.11.02 Figure 5-8: Arria 10 Gen1 and Gen2 x1 Channel Placement fPLL1 PMA Channel 5 PCS Channel 5 PMA Channel 4 PCS Channel 4 ATX1 PLL Hard IP...
  • Page 52 Channel Placement and fPLL and ATX PLL Usage for the Gen3 Data Rate The following figures illustrate the x1, x2, x4, and x8 channel placement for the Arria 10 Hard IP for PCI Express. Gen3 variants must initially train at the Gen1 data rate. Consequently, Gen3 variants require an fPLL to generate the 2.5 and 5.0 Gbps clocks, and an ATX PLL to generate the 8.0 Gbps clock.
  • Page 53 PCS Channel 2 PMA Channel 1 PCS Channel 1 ATX0 PLL PMA Channel 0 PCS Channel 0 Master indicates the location of the master clock generation block (CGB) Physical Layout of Hard IP In Arria 10 Devices Altera Corporation Send Feedback...
  • Page 54 Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
  • Page 55 UG-01145_avmm_dma Arria 10 DMA Avalon-MM DMA Interface to the Application Layer 2015.11.02 Figure 6-1: Avalon-MM DMA Bridge with Internal Descriptor Controller Hard IP for PCI Express Using Avalon-MM with DMA refclk RdDmaWrite_o Clocks coreclkout_hip RdDmaAddress_o[63:0] Read DMA Avalon-MM : RdDmaWriteData[<w> -1:0]...
  • Page 56 The Read DMA module sends memory read TLPs upstream. It writes the completion data to an external Avalon-MM interface through the high throughput Read Master port. This port operates on descriptors the IP core receives from the DMA Descriptor Controller. IP Core Interfaces Altera Corporation Send Feedback...
  • Page 57 When asserted, indicates that the memory is not ready to RdDmaWaitRequest_i receive data. Frequent assertion may incoming packet processing to stop until deasserts. RdDmaWaitRequest_i Figure 6-3: Read DMA Avalon-MM Master Writes Data to FPGA Memory read_data_mover\.RdDmaAddress_o[63:0] read_data_mover\.RdDmaBurstCount_o[4:0] read_data_mover\.RdDmaWrite_o read_data_mover\.RdDmaWaitRequest_i read_data_mover\.RdDmaWriteData_o[255:0] read_data_mover\.RdDmaByteEnable_o[31:0] IP Core Interfaces Altera Corporation Send Feedback...
  • Page 58 The RX Master module translates read and write TLPs received from the PCIe link to Avalon-MM requests for Qsys components connected to the interconnect. This module allows other PCIe components, including host software, to access other Avalon-MM slaves connected in the Qsys system. IP Core Interfaces Altera Corporation Send Feedback...
  • Page 59 • 256: for the bursting 256-bit Avalon-MM interface Input RxmReadDataValid_<n>_ When asserted, indicates that RxmReadData_i[31:0]is i[31:0] valid. Input When asserted indicates that the control register access Avalon- RxmWaitRequest_<n>_i MM slave port is not ready to respond. IP Core Interfaces Altera Corporation Send Feedback...
  • Page 60 Address width of accessible PCIe memory space. Input Specifies the valid bytes for a write command. TxsByteEnable_i[3:0] Output Specifies the read completion data. TxsReadData_o[<w>- 1:0] When asserted, indicates that is valid. Output TxsReadDataValid_o TxsReadData_o[31:0] IP Core Interfaces Altera Corporation Send Feedback...
  • Page 61 2. Bits 1 and 0 are 0. To read or write individual bytes of a dword, use byte enables. For example, to write bytes 0 and 1, set CraByteEnable_i[3:0]= 4'b0011 IP Core Interfaces Altera Corporation Send Feedback...
  • Page 62 DMA Descriptor Format table below for bit definitions. Input When asserted, indicates that is valid. WrAstRxValid_i WrAstRxData_i[159:0] Output When asserted, indicates that the Write DMA module engine is WrAstRxReady_o ready to receive a new descriptor. IP Core Interfaces Altera Corporation Send Feedback...
  • Page 63 High-order 32 bits of the destination address. Destination High Address [145:128] Specifies DMA length in dwords. The length must be greater DMA Length than 0. The maximum length is 1 MB - 4 bytes. IP Core Interfaces Altera Corporation Send Feedback...
  • Page 64 The Read Descriptor Controller Avalon-MM master port drives the TX Avalon-MM slave port. This port drives single dword transactions to the Arria 10 Avalon-MM DMA for PCIe. The Read Descriptor Controller uses this port to write descriptor status to the PCIe domain and possibly to MSI when MSI messages are enabled.
  • Page 65 This port is available when you select the internal Descriptor Controller. It receives the Read DMA descriptors which are fetched by Read DMA. . Connect the port to the Read DMA Avalon-MM master port. IP Core Interfaces Altera Corporation Send Feedback...
  • Page 66 When asserted, indicates that the Avalon-MM slave device is not WrDTSWaitRequest_o ready to respond. Input Drives the 128- or 256-bit write data. WrDTSWriteData_ i[255:0] or [127:0] When asserted, indicates a write transaction. Input WrDTSWrite_i IP Core Interfaces Altera Corporation Send Feedback...
  • Page 67 Configuration via Protocol (CvP) requires this signal. For more information about CvP refer to Configuration via Protocol (CvP). Arria 10 devices can have up to 4 instances of the Hard IP for PCI Express. Each instance has its own signal. You...
  • Page 68 NPERSL0 For maximum use of the Arria 10 device, Altera recommends that you use the bottom left Hard IP first. This is the only location that supports CvP over a PCIe link. If your design does not require CvP, you may select other Hard IP blocks.
  • Page 69 Application Layer should generate an internal reset signal that is asserted for at least 32 cycles. Altera does not rigorously test or verify debug signals. Only use debug signals to observe behavior. Do not use debug signals to drive custom logic.
  • Page 70 • 4’b1000: 8 lanes Output LTSSM state: The LTSSM state machine encoding defines the ltssmstate[4:0] following states: • 00000: Detect.Quiet • 00001: Detect.Active • 00010: Polling.Active • 00011: Polling.Compliance • 00100: Polling.Configuration • 00101: Polling.Speed IP Core Interfaces Altera Corporation Send Feedback...
  • Page 71 • 2’b01: Some time later, the parity error is detected by the TX Data Link Layer which drives 2’b01 to indicate the error. Reset the IP core when this error is detected. Contact Altera technical support if resetting becomes unworkable.
  • Page 72 PCI Express Card Electromechanical Specification 2.0 • • Configuration via Protocol (CvP) Implementation in Altera FPGAs User Guide MSI Interrupts for Endpoints The MSI interrupt notifies the host when a DMA operation has completed. After the host receives this interrupt, it can poll the DMA read or write status table to determine which entry or entries have the done bit set.
  • Page 73 Output 16-bit read data. is valid on the hip_reconfig_ hip_reconfig_readdata[15:0] third cycle after the assertion of readdata[15:0] hip_reconfig_read Input Write signal. hip_reconfig_write IP Core Interfaces Altera Corporation Send Feedback...
  • Page 74 D2 D3 4 clks avmm_rd avmm_rdata[15:0] For a detailed description of the Avalon-MM protocol, refer to the Avalon Memory Mapped Interfaces chapter in the Avalon Interface Specifications. Related Information Avalon Interface Specifications IP Core Interfaces Altera Corporation Send Feedback...
  • Page 75 Receive input. These signals are the serial inputs of lanes 7–0. rx_in[7:0] Refer to Pin-out Files for Altera Devices for pin-out tables for all Altera devices in .pdf, .txt, and .xls formats. Transceiver channels are arranged in groups of six. For GX devices, the lowest six channels on the left side of the device are labeled GXB_L0, the next group is GXB_L1, and so on.
  • Page 76 • 2'b01: Gen2 • 2'b10: Gen3 • 2'b11: Reserved For Gen3 operation, indicates the start of a block in the receive Input rxblkst0 direction. Input Receive data. This bus receives data on lane <n>. rxdata0[31:0] IP Core Interfaces Altera Corporation Send Feedback...
  • Page 77 • 5’b01100: Recovery.Rcvlock • 5’b01101: Recovery.Rcvconfig • 5’b01110: Recovery.Idle • 5’b 01111: L0 • 5’b10000: Disable • 5’b10001: Loopback.Entry • 5’b10010: Loopback.Active • 5’b10011: Loopback.Exit • 5’b10100: Hot.Reset • 5’b10101: L0s • 5’b11001: L2.transmit.Wake IP Core Interfaces Altera Corporation Send Feedback...
  • Page 78 Training Sequences (TS). You do not need to change this value. Transmit detect receive <n>. This signal tells the PHY layer to Output txdetectrx0 start a receive detection operation or to begin loopback. IP Core Interfaces Altera Corporation Send Feedback...
  • Page 79 When asserted, indicates full swing for the transmitter voltage. txswing0 When deasserted indicates half swing. Output For Gen3 operation, specifies the block type. The following txsynchd0[1:0] encodings are defined: • 2'b01: Ordered Set Block • 2'b10: Data Block IP Core Interfaces Altera Corporation Send Feedback...
  • Page 80 Arria 10 Development Kit Conduit Interface The Arria 10 Development Kit conduit interface signals are optional signals that allow you to connect your design to the Arria 10 FPGA Development Kit. Enable this interface by selecting Enable Arria 10 IP Core Interfaces...
  • Page 81 UG-01145_avmm_dma 6-28 Arria 10 Development Kit Conduit Interface 2015.11.02 FPGA Development Kit connection on the Configuration, Debug, and Extension Options tab of the component GUI. The output port includes signals useful for debugging. devkit_status Table 6-24: Signal Name Direction Description...
  • Page 82 Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
  • Page 83 The Type 1 Configuration Space is not available for the Avalon-MM with DMA interface 0x004 Status, Command Type 0 Configuration Space Header Type 1 Configuration Space Header The Type 1 Configuration Space is not available for the Avalon-MM with DMA interface Registers Altera Corporation Send Feedback...
  • Page 84 Type 0 Configuration Space Header Prefetchable Limit Upper 32 Bits Type 1 Configuration Space Header 0x030 I/O Limit Upper 16 Bits, I/O Base Upper 16 Type 0 Configuration Space Header Bits Type 1 Configuration Space Header Registers Altera Corporation Send Feedback...
  • Page 85 Uncorrectable Error Mask Register Uncorrectable Error Mask Register 0x80C Uncorrectable Error Severity Register Uncorrectable Error Severity Register 0x810 Correctable Error Status Register Correctable Error Status Register 0x814 Correctable Error Mask Register Correctable Error Mask Register Registers Altera Corporation Send Feedback...
  • Page 86 BAR Registers 0x01C BAR Registers 0x020 BAR Registers 0x024 Reserved 0x028 Subsystem Device ID Subsystem Vendor ID 0x02C Expansion ROM Base Address 0x030 Reserved Capabilities Pointer 0x034 0x038 Reserved 0x03C 0x00 Interrupt Pin Interrupt Line Registers Altera Corporation Send Feedback...
  • Page 87 Figure 7-3: MSI Capability Structure 24 23 16 15 Message Control 0x050 Configuration MSI Control Status Next Cap Ptr Capability ID Register Field Descriptions 0x054 Message Address 0x058 Message Upper Address 0x05C Reserved Message Data Registers Altera Corporation Send Feedback...
  • Page 88 Figure 7-7: PCI Express Capability Structure - Byte Address Offsets and Layout In the following table showing the PCI Express Capability Structure, registers that are not applicable to a device are reserved. Note: The Avalon-MM with DMA interface does not support Root Ports. Registers Altera Corporation Send Feedback...
  • Page 89 Figure 7-8: VSEC Registers This extended capability structure supports Configuration via Protocol (CvP) programming and detailed internal error reporting. 20 19 16 15 0x200 Next Capability Offset Version Altera-Defined VSEC Capability Header VSEC VSEC ID 0x204 VSEC Length Revision Altera-Defined, Vendor-Specific Header 0x208...
  • Page 90 UG-01145_avmm_dma Altera-Defined VSEC Registers 2015.11.02 Table 7-2: Altera‑Defined VSEC Capability Register, 0x200 The Altera-Defined Vendor Specific Extended Capability. This extended capability structure supports Configuration via Protocol (CvP) programming and detailed internal error reporting. Bits Register Description Value Access [15:0] PCI Express Extended Capability ID. Altera-defined value for 0x000B VSEC Capability ID.
  • Page 91 FPGA control block, checked by software to determine if there was an error during configuration. [18] . Reflects the value of this signal from the Variable CVP_CONFIG_READY FPGA control block, checked by software during programming algorithm. [17:0] Reserved Variable Registers Altera Corporation Send Feedback...
  • Page 92 [7:3] Reserved. . Request that the FPGA control block 1’b0 CVP_FULLCONFIG reconfigure the entire FPGA including the Arria 10 Hard IP for PCI Express, bring the PCIe link down. . Selects between PMA and fabric clock when 1’b0 HIP_CLK_SEL USER_ = 1 and = 1.
  • Page 93 Read Write Sticky meaning the value is retained after a soft reset of the IP core. Bits Register Description Reset Value Access [31:12] Reserved. 1b’0 [11] Mask for RX buffer posted and completion overflow error. 1b’1 [10] Reserved 1b’0 Registers Altera Corporation Send Feedback...
  • Page 94 When set, indicates an RX buffer overflow condition in a RW1CS posted request or Completion [10] Reserved. When set, indicates a parity error was detected on the Configu‐ RW1CS ration Space to TX bus interface Registers Altera Corporation Send Feedback...
  • Page 95 Correctable Internal Error Mask Errors. This register is for debug only. Bits Register Description Reset Value Access [31:7] Reserved. Mask for Corrected Internal Error reported by the Application Layer. Mask for configuration error detected in CvP mode. Registers Altera Corporation Send Feedback...
  • Page 96 PCI Express main memory. The DMA Descriptor Controller instructs the Read DMA to copy the table to its own internal FIFO. When the DMA Descriptor Controller is instantiated as a separate component, it drives table entries on the buses. RdDmaRxData_i[159:0] WrDmaRxData_i[159:0] Registers Altera Corporation Send Feedback...
  • Page 97 When the DMA Descriptor Controller is embedded in the Avalon-MM DMA bridge, it drives this information on an internal conduit interface. Figure 7-9: Block Diagram for Internal Descriptor Controller Altera FPGA Qsys System Hard IP for PCIe Using Avalon-MM Interface...
  • Page 98 <n-1> and <n -2> have also completed. You must request the completion status for every descriptor by writing the descriptor ID for every descriptor to RD_DMA_LAST_PTR . Many commercial system Root Ports do return out-of-order Read Completions based WR_DMA_LAST_PTR on optimized accesses to host memory channels. Registers Altera Corporation Send Feedback...
  • Page 99 Avalon-MM address of the Descriptor Controller's Read Descriptor Table Avalon-MM Slave Port as seen by the Read DMA Avalon-MM Master Port. You must program this register after program‐ ming the upper 32 bits at offset 0x8. Registers Altera Corporation Send Feedback...
  • Page 100 Set to the number of descriptors - 1. By default, is set to RD_TABLE_SIZE 127.This value specifies the last . To change the Descriptor ID RC Read Status and Descriptor Base (Low) base address, all descriptors specified by must be exhausted. RD_TABLE_SIZE Registers Altera Corporation Send Feedback...
  • Page 101 Avalon-MM address of the Descriptor Controller's Write Descriptor Table Avalon-MM Slave Port as seen by the Read DMA Avalon-MM Master Port. Software must program this register after programming the upper 32-bit register at offset 0x10C. Registers Altera Corporation Send Feedback...
  • Page 102 0x0118 [31:1] Reserved. WR_CONTROL . When set, the Descriptor Done Controller writes the bit for each Done descriptor in the status table. The Descriptor Controller sends a single MSI interrupt after the final descriptor completes. Registers Altera Corporation Send Feedback...
  • Page 103 Table 7-18: Write Descriptor Table Format Register Name Address Description Offset 0x00 Lower dword of the write DMA source address. WR_RC_LOW_SRC_ADDR Specifies the address in the Avalon-MM domain from which the Write DMA fetches data. Registers Altera Corporation Send Feedback...
  • Page 104 Figure 7-11: Data Blocks to Transfer from PCIe to Avalon-MM Address Space Using Read DMA PCIe System Memory Avalon-MM Memory Addr 0x1_2000_0000 256 KB 1 MB Addr 0x5000_0000 Addr 0x2000_0000 512 KB 256 KB Addr 0x1000_0000 Addr 0x1000_0000 1 MB 512 KB Addr 0x0001_0000 Registers Altera Corporation Send Feedback...
  • Page 105 Program 0x1000_0000 to source address 0xF000_02004. This is the upper 32 bits of the source address. b. Program 0x0000_0000 to source address 0xF000_0200. This is the lower 32 bits of the source address. c. Program 0x5000_0000 to destination address 0xF000_020C. Registers Altera Corporation Send Feedback...
  • Page 106 0xF000_0008. If the system supports out-of-order Read Completions, the Descriptor Controller may complete descriptors out of order. In such systems, you must use this method of requesting status for each descriptor. Software must check for status for every descriptor. done done Registers Altera Corporation Send Feedback...
  • Page 107 8 requests with 8 different tags. The Read Completions can come back in any order. The Read DMA Avalon-MM master port writes the Read Completions to the correct locations, based on the tags. Registers Altera Corporation Send Feedback...
  • Page 108 0.For Gen2 variants, this bit is set to 1. 14'h0010 Base/Primary Command register for the PCI cfg_prm_cmd[15:0] Configuration Space. 14'h0014 Root control and status register of the PCI-Express cfg_root_ctrl[7:0] capability. This register is only available in Root Port mode. Registers Altera Corporation Send Feedback...
  • Page 109 Type1 Configuration Space. This register is only available in Root Port mode. 14'h0044 The lower 32 bits of the prefetchable limit registers cfg_pr_lim_low[31:0] of the Type1 Configuration Space. This register is only available in Root Port mode. Registers Altera Corporation Send Feedback...
  • Page 110 : Mapping for TC5. cfg_tcvcmap[17:15] • : Mapping for TC6. cfg_tcvcmap[20:18] • : Mapping for TC7. cfg_tcvcmap[23:21] 14'h005C is message data for MSI. cfg_msi_data[15:0] cfg_msi_data[15:0] 14'h0060 Bus/Device Number captured by or programmed in cfg_busdev[12:0] the Hard IP. Registers Altera Corporation Send Feedback...
  • Page 111 • 5'b: 11101: Recovery.Equalization, Phase 2 • 5'b: 11110: recovery.Equalization, Phase 3 14'h0068 Indicates the current speed of the PCIe link. The current_speed_reg[1:0] following encodings are defined: • 2b’00: Undefined • 2b’01: Gen1 • 2b’10: Gen2 • 2b’11: Gen3 Registers Altera Corporation Send Feedback...
  • Page 112 Lane Active Mode: This signal indicates the number lane_act_reg[3:0] of lanes that configured during link training. The following encodings are defined: • 4’b0001: 1 lane • 4’b0010: 2 lanes • 4’b0100: 4 lanes • 4’b1000: 8 lanes Registers Altera Corporation Send Feedback...
  • Page 113 Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
  • Page 114 3. The Hard IP for PCI Express deasserts the output to the Application Layer. reset_status 4. The deasserts cycles after is released. altpcied_<device>v_hwtcl.sv app_rstn pld_clk reset_status Arria 10 Reset and Clocks Altera Corporation Send Feedback...
  • Page 115 IP core deasserts the input to the TX transceiver. npor npor_serdes 2. The SERDES reset controller waits for to be stable for a minimum of 127 cycles pll_locked pld_clk before deasserting tx_digitalreset. Arria 10 Reset and Clocks Altera Corporation Send Feedback...
  • Page 116 Figure 8-5: Clock Domains and Clock Generation for the Application Layer The following illustrates the clock domains when using to drive the Application Layer coreclkout_hip and the of the IP core. The Altera-provided example design connects to the pld_clk coreclkout_hip . However, this connection is not mandatory.
  • Page 117 Table 8-2: Clock Summary Name Frequency Clock Domain 62.5, 125 or 250 MHz Avalon-ST interface between the Transaction and coreclkout_hip Application Layers. 125 or 250 MHz Application and Transaction Layers. pld_clk Arria 10 Reset and Clocks Altera Corporation Send Feedback...
  • Page 118 UG-01145_avmm_dma Clock Summary 2015.11.02 Name Frequency Clock Domain 100 MHz SERDES (transceiver). Dedicated free running input refclk clock to the SERDES block. Arria 10 Reset and Clocks Altera Corporation Send Feedback...
  • Page 119 Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
  • Page 120 This error occurs when the replay number rolls over. Data Link Layer protocol Uncorrectable(fatal) This error occurs when a sequence number specified by the Ack/Nak block in the Data Link Layer ( AckNak_Seq_ does not correspond to an unacknowledged TLP. Num) Error Handling Altera Corporation Send Feedback...
  • Page 121 • A memory transaction when the Memory Space Enable bit (bit [1] of the PCI Command register at Configuration Space offset 0x4) is set to 0. • A poisoned configuration write request ( CfgWr0 Error Handling Altera Corporation Send Feedback...
  • Page 122 The Application Layer can detect and report other unexpected completion conditions using the cpl_ signal. For example, the Application Layer can err[2] report cases where the total length of the received successful completions do not match the original read request length. Error Handling Altera Corporation Send Feedback...
  • Page 123 How the Endpoint handles a particular error depends on the configuration registers of the device. Refer to the PCI Express Base Specification 3.0 for a description of the device signaling and logging for an Endpoint. Error Handling Altera Corporation Send Feedback...
  • Page 124 Poisoned packets received by the Hard IP block are passed to the Application Layer. Poisoned transmit TLPs are similarly sent to the link. Related Information PCI Express Base Specification 3.0 Uncorrectable and Correctable Error Status Bits The following section is reprinted with the permission of PCI-SIG. Copyright 2010 PCI-SIG. Error Handling Altera Corporation Send Feedback...
  • Page 125 16 15 14 13 12 11 9 Rsvd Rsvd Rsvd Header Log Overflow Status Corrected Internal Error Status Advisory Non-Fatal Error Status Replay Timer Timeout Status REPLAY_NUM Rollover Status Bad DLLP Status Bad TLP Status Receiver Error Status Error Handling Altera Corporation Send Feedback...
  • Page 126 Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
  • Page 127 UG-01145_avmm_dma 10-2 IP Core Architecture 2015.11.02 Figure 10-1: Arria 10 Avalon-MM DMA for PCI Express Clock & Reset Selection Configuration Block PHY IP Core for Hard IP for PCI Express DMA Read Configuration via PCIe Link (CvP) PCI Express (PIPE)
  • Page 128 • Gen3 x2 • Gen3 x4 • Gen3 x8 Related Information Arria 10 DMA Avalon-MM DMA Interface to the Application Layer on page 6-1 Clocks and Reset The PCI Express Base Specification requires an input reference clock, which is called in this design.
  • Page 129 • The Gen1, Gen2, and Gen3 simulation models support PIPE and serial simulation. • For Gen3, the Altera BFM bypasses Gen3 Phase 2 and Phase 3 Equalization. However, Gen3 variants can perform Phase 2 and Phase 3 equalization if instructed by a third-party BFM.
  • Page 130 • Retry Buffer—The retry buffer stores TLPs and retransmits all unacknowledged packets in the case of NAK DLLP reception. In case of ACK DLLP reception, the retry buffer discards all acknowledged packets. IP Core Architecture Altera Corporation Send Feedback...
  • Page 131 • Serializing and deserializing data • Operating the PIPE 3.0 Interface • Implementing auto speed negotiation (Gen2 and Gen3) • Transmitting and decoding the training sequence • Providing hardware autonomous speed control • Implementing auto lane reversal IP Core Architecture Altera Corporation Send Feedback...
  • Page 132 The Physical Layer integrates both digital and analog elements. Intel designed the PIPE interface to separate the MAC from the PHY. The Arria 10 Hard IP for PCI Express complies with the PIPE interface specification. IP Core Architecture...
  • Page 133 DLL. Arria 10 Avalon-MM DMA for PCI Express The Arria 10 Avalon-MM DMA for PCI Express IP Core includes highly efficient Read DMA, Write DMA, and DMA Descriptor Controller modules. The example design described in the Getting Started with the Avalon-MM DMA chapter includes a Linux software driver for these DMA modules.
  • Page 134 Embedding the DMA Descriptor simplifies the design. Altera recommends that you embed the DMA Descriptor Controller in the Avalon-MM DMA bridge if you do not plan to modify it. Refer to Getting Started with the Arria 10 Avalon-MM DMA for an example that includes the embedded DMA Descriptor Controller.
  • Page 135 The RX burst master supports a maximum read request of 4096 bytes, which is the maximum allowed by the PCI Express specification. If you plan to modify or replace the DMA Descriptor Controller, Altera recommends that you instantiate it separately. The following block diagram illustrates this configuration. Your descriptor controller must interface to the DMA read and DMA write modules that are always part of the PCI Express Avalon-MM DMA bridge.
  • Page 136 UG-01145_avmm_dma 10-11 Arria 10 Avalon-MM DMA for PCI Express 2015.11.02 The DMA modules shown in the block diagrams implement the following functionality: • Read DMA –The Read DMA module sends memory read TLPs upstream and writes the completion data to external Avalon-MM components using the high throughput read master port. It follows the PCI Express Base Specification rules concerning tags, flow control credits, completion timeouts, read completion boundary, and 4 KByte boundaries.
  • Page 137 Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
  • Page 138 .sdc for the Arria 10 Hard IP for PCIe IP core. Example 11-1: SDC Timing Constraints Required for the Arria 10 Hard IP for PCIe and Design Example # Constraints required for the Arria 10 Hard IP for PCI Express # derive_pll_clock is used to calculate all clock derived # from PCIe refclk.
  • Page 139 Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
  • Page 140 Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
  • Page 141 Added note in Physical Layout of Hard IP In Arria 10 Devices explain Arria 10 design constraint that requires that if the lower HIP on one side of the device is configured with a Gen3 x4 or Gen3 x8 IP...
  • Page 142 • Added instructions for Quartus II compilation. 2014.08.18 14.0 Arria 10 Made the following changes to the Arria 10 Avalon-MM DMA for PCI Express IP core: • Revised programming model for the Descriptor Controller. • Added simulation log file, altpcie_monitor_a10_dlhip_tlp_file_log.log...
  • Page 143 • Removed 125 MHz clock as optional frequency in Arria 10 refclk devices. Arria 10 devices support a 100 MHz reference clock as specified by the PCI Express Base Specification, Rev 3.0 • Corrected values for Maximum payload size parameter. The sizes available are 128 or 256 bytes.
  • Page 144 • Optional Features • Debugging • Throughput Optimization 2013.12.02 13.1 Arria 10 Initial release. How to Contact Altera To locate the most up-to-date information about Altera products, refer to the following table. Contact Contact Method Address Technical support Website www.altera.com/support Website www.altera.com/training...
  • Page 145 UG-01145_avmm_dma Typographic Conventions 2015.11.02 Contact Contact Method Address Note to Table: 1. You can also contact your local Altera sales office or sales representative. Related Information Technical Support • Technical Training • Customer Training • Product Documentation • • Non-Technical Support (general) Licensing •...
  • Page 146 A caution calls attention to a condition or possible situation that can damage or destroy the product or your work. A warning calls attention to a condition or possible situation that can cause you injury. Additional Information Altera Corporation Send Feedback...
  • Page 147 The Subscribe button links to the Email Subscription Management Center page of the Altera website, where you can sign up to receive update notifications for Altera documents. The Feedback icon allows you to submit feedback to Altera about the document. Methods for collecting feedback vary as appropriate for each document.