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EN 20
7.
TPM4.1E LA
7. Circuit Descriptions
Index of this chapter:
7.1 Introduction
7.2 Power Architecture
7.3 T-CON Architecture
Notes:
•
Only new circuits (circuits that are not published recently)
are described.
•
Figures can deviate slightly from the actual situation, due
to different set executions.
•
For a good understanding of the following circuit
descriptions, please use the wiring, block (see chapter
9. Block Diagrams) and circuit diagrams (see chapter
10. Circuit Diagrams and PWB Layouts).Where necessary,
you will find a separate drawing for clarification.
MM Tuner
D-SUB
Side AV
Side S -Video
SCART 1
YPbPr 1
YPbPr 1 Audio
AV IN
YPbPr 2
Monitor Out
SCART 2
Side AV Audio
AV Audio
PC Audio
YPbPr 2 Audio
Remark : Reserve only for iTV function
2010-Jun-18
Circuit Descriptions
TV_CVBS
(CVBS 0P)
SIF_P
HDMI 1
HDMI 2
RP,GP,BP
CVBS1P
TV OUT
Audio out(AR2, AL2)
MAX9728
Audio In
CVBS2P
Y,Pb,Pr 1
CVBS3P
Y,Pb,Pr 2
CVBS out
Audio out(AR3, AL3)
MAX9728
CVBS_SC0
74HC4052D
Audio In
MUX
Figure 7-1 Architecture of TPM4.1E LA
7.1
Introduction
The TPM4.1E LA chassis is using the MT8222 for main
processing.
7.1.1
Implementation
A key component of this chassis is the TCON TL2428MC
7.1.2
TPM4.1E LA Architecture Overview
•
For details about the chassis diagrams refer to
chapter 10. Circuit Diagrams and PWB Layouts.
An overview of the TPM4.1E LA architecture can be found
in
Figure
24C32
24C02
DSUB EDID
NVRAM
WT6703
STDBY MCU
I2C
I2C
MT8222
AR1,AL1
DAC
AUDR, AUDL
CS4334
MAX9728
HP
TPA3110D
2 × (2P)
L-R Speaker
7-1.
24C02
DVI EDID
SPI Flash
ROM / 4M
SPI
DDR
Tcon
TTL/LVDS
TL2428
MC
UART1
Com Pair
Cloning
(iTV-1)
Video I/F
(5P)
(iTV-2)
(7P)
IR Board
(3P)
Key Board
LIPS/PS
10P
control
Side USB
18870_210_100308.eps
LCD
Panel
100308
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