T O D E T E R M I N E W H E N A C O M M A N D S E Q U E N C E I S C O M P L E T E; U S I N G * O P C T O S I G N A L W H E N D A T A I S I N T H E O U T P U T B U F F E - Agilent Technologies E3633A Operating Manual

Chapter 4 Remote Interface Reference
The SCPI Status Registers
To Determine When a Command Sequence is Completed
Send a device clear message to clear the power supply's output buffer (e.g.,
1
CLEAR 705
).
Clear the event registers with the
2
Enable the "operation complete" bit (bit 0) in the Standard Event register by
3
*ESE 1
executing the
*OPC?
Send the (operation complete query) command and enter the result to
4
ensure synchronization.
Execute your command string to program the desired configuration, and then
5
*OPC
execute the (operation complete) command as the last command. When
the command sequence is completed, the "operation complete" bit (bit 0) is
set in the Standard Event register.
Use a serial poll to check to see when bit 5 (standard event) is set in the Status
6
Byte summary register. You could also configure the power supply for an
SRQ interrupt by sending
Using *OPC to Signal When Data is in the Output Buffer
G e n e r a l l y , i t i s b e s t t o u s e t h e " o p e r a t i o n c o m p l e t e " b i t ( b i t 0 ) i n t h e S t a n d a r d
E v e n t r e g i s t e r t o s i g n a l w h e n a c o m m a n d s e q u e n c e i s c o m p l e t e d . T h i s b i t i s
s e t i n t h e r e g i s t e r a f t e r a n
*OPC
a f t e r a c o m m a n d w h i c h l o a d s a m e s s a g e i n t h e p o w e r s u p p l y ' s o u t p u t
b u f f e r ( q u e r y d a t a ) , y o u c a n u s e t h e " o p e r a t i o n c o m p l e t e " b i t t o d e t e r m i n e
w h e n t h e m e s s a g e i s a v a i l a b l e . H o w e v e r , i f t o o m a n y m e s s a g e s a r e g e n e r a t e d
*OPC
b e f o r e t h e c o m m a n d e x e c u t e s ( s e q u e n t i a l l y ) , t h e o u t p u t b u f f e r w i l l f i l l
a n d t h e p o w e r s u p p l y w i l l s t o p p r o c e s s i n g c o m m a n d s .
*CLS
(clear status) command.
command.
*SRE 32
(Status Byte enable register, bit 5).
*OPC
c o m m a n d h a s b e e n e x e c u t e d . I f y o u s e n d
4
97