The Status Byte Register - Agilent Technologies E3633A Operating Manual

Chapter 4 Remote Interface Reference
The SCPI Status Registers
The Standard Event register is cleared when:
*CLS
• Y o u e x e c u t e t h e
• Y o u q u e r y t h e e v e n t r e g i s t e r u s i n g t h e
c o m m a n d .
F o r e x a m p l e , 2 8 ( 4 + 8 + 1 6 ) i s r e t u r n e d w h e n y o u h a v e q u e r i e d t h e s t a t u s o f
t h e S t a n d a r d E v e n t r e g i s t e r , Q Y E , D D E , a n d E X E c o n d i t i o n s h a v e o c c u r r e d .
The Standard Event Enable register is cleared when:
*ESE 0
• Y o u e x e c u t e t h e
• Y o u t u r n o n t h e p o w e r a n d h a v e p r e v i o u s l y c o n f i g u r e d t h e p o w e r s u p p l y
*PSC 1
u s i n g t h e c o m m a n d .
• T h e e n a b l e r e g i s t e r w i l l n o t b e c l e a r e d a t p o w e r - o n i f y o u h a v e p r e v i o u s l y
c o n f i g u r e d t h e p o w e r s u p p l y u s i n g t h e

The Status Byte Register

T h e S t a t u s B y t e s u m m a r y r e g i s t e r r e p o r t s c o n d i t i o n s f r o m t h e o t h e r s t a t u s
r e g i s t e r s . Q u e r y d a t a t h a t i s w a i t i n g i n t h e p o w e r s u p p l y ' s o u t p u t b u f f e r i s
i m m e d i a t e l y r e p o r t e d t h r o u g h t h e " M e s s a g e A v a i l a b l e " b i t ( b i t 4 ) o f S t a t u s B y t e
r e g i s t e r . B i t s i n t h e s u m m a r y r e g i s t e r a r e n o t l a t c h e d . C l e a r i n g a n e v e n t r e g i s t e r
w i l l c l e a r t h e c o r r e s p o n d i n g b i t s i n t h e S t a t u s B y t e s u m m a r y r e g i s t e r . R e a d i n g
a l l m e s s a g e s i n t h e o u t p u t b u f f e r , i n c l u d i n g a n y p e n d i n g q u e r i e s , w i l l c l e a r t h e
m e s s a g e a v a i l a b l e b i t .
Table 4-5. Bit Definitions – Status Byte Summary Register
Bit Decimal
Value
0-2 Not Used 0
3 QUES
8
4 MAV 16
5 ESB
32
6 RQS 64
7 Not Used 0
94
( c l e a r s t a t u s ) c o m m a n d .
*ESR?
( E v e n t S t a t u s r e g i s t e r )
c o m m a n d .
*PSC 0
Definition
Always set to 0.
One or more bits are set in the questionable status
register (bits must be "enabled" in the enable register).
Data is available in the power supply output buffer.
One or more bits are set in the standard event register
(bits must be "enabled" in the enable register).
The power supply is requesting service (serial poll).
Always set to 0.
c o m m a n d .