Ivy Bridge Processor 2/7 - Clevo W170ER Service Manual

Schematic Diagrams

Ivy Bridge Processor 2/7

PU/PD for JTAG signals
Sheet 3 of 51
Ivy Bridge
Processor 2/7
Buffered reset to CPU
24,30
B - 4 Ivy Bridge Processor 2/7
Ivy Bridge Processor 2/7 ( CLK,MISC,JTAG )
1.05VS_VTT
*51_04 R325 XDP_PREQ#
RN11 56_8P4R_04
8 1 XDP_TDI_R
7 2
XDP_TMS
6 3 XDP_TDO_R
5 4 XDP_TCLK
51_04 R328 XDP_TRST#
25 H_SNB_IVB#
3.3VS
R25 1K_04 XDP_DBR_R
H_CATERR#
If PROCHOT# is not used,
then it must be terminated
R31
21,25,36 H_PECI
with a 56-£[ +-5% pull-up
resistor to 1.05VS_VTT .
H_PROCHOT# R46 56_1%_04 H_PROCHOT#_D
42,44 H_PROCHOT#
25 H_THRMTRIP#
22 H_PM_SY NC
R32 *10mil_short H_CPUPWRGD_R
25 H_CPUPWRGD
PMSY S_PWRGD_BUF R48 130_1%_04 VDDPWRGOOD_R
1.05VS_VTT
BUF_CPU_RST#
3.3VS
R35
75_04
R34
BUF_CPU_RST#
R36 43.2_1%_04
10K_04
D
Q2B
5
G MTDN7002ZHS6R
S
D
2
G Q2A
PLT_RST#
MTDN7002ZHS6R
S
R37 *1.5K_1%_04
R51 C134
R28
100K_04 68p_50V_NPO_04
*750_1%_04
U17B
A28
BCLK
C26 A27
PROC_SELECT# BCLK#
AN34
SKTOCC#
A16
DPLL_REF_CLK
A15
DPLL_REF_CLK#
AL33
CATERR#
AN33 R8 CPUDRAMRST#
*10mil_short
PECI SM_DRAMRST#
AL32 AK1
SM_RCOMP_0
PROCHOT# SM_RCOMP[0]
A5 SM_RCOMP_1
SM_RCOMP[1]
A4 SM_RCOMP_2
SM_RCOMP[2]
AN32
THERMTRIP#
AP29 XDP_PRDY#
PRDY #
AP27 XDP_PREQ#
PREQ#
AR26
XDP_TCLK
TCK
AR27 XDP_TMS
TMS
AM34 AP30 XDP_TRST#
PM_SYNC TRST#
AR28
XDP_TDI_R
TDI
AP26 XDP_TDO_R
TDO
AP33
UNCOREPWRGOOD
AL35
XDP_DBR_R
DBR#
V8
SM_DRAMPWROK
AT28
BPM#[0]
AR29
BPM#[1]
AR30
BPM#[2]
AR33 AT30
RESET# BPM#[3] AP32
2011.10.25
BPM#[4]
AR31
BPM#[5]
AT31
BPM#[6]
AR32
BPM#[7]
PZ98821-364B-01F
H_PROCHOT#
Q3
G C132
36 H_PROCHOT#_EC
MTN7002ZHS3
R44 47p_50V_NPO_04
100K_04
CAD Note: Capacitor need to be placed
close to buffer output pin
2,6,11,18,20,21,22,24,25,26,27,29,30,31,35,37,39,40,41
9,10,11,20,21,22,23,24,25,26,27,29,30,32,33,34,35,36,37,42,44
Processor Pullups/Pull downs
H_PROCHOT#
R49 62_04
H_CPUPWRGD_R R33 10K_04
TRACE WIDTH 10MIL, LENGTH <500MILS
CLK_EXP_P 21
CLK_EXP_N 21
CLK_DP_P 21
CLK_DP_N 21 DDR3 Compensation Signals
SM_RCOMP_0
R18 140_1%_04
SM_RCOMP_1 R317 25.5_1%_04
SM_RCOMP_2
R318 200_1%_04
S3 circuit:- DRAM PWR GOOD logic
3.3V 3.3V
C137
R57 R58
1.5VS_CPU
R38
200_1%_04
1
22 PM_DRAM_PWRGD
4 PMSY S_PWRGD_BUF
2
22,39 1.8VS_PWRGD
U5
*MC74VHC1G08DFT1G R45
*39_04
R50 *10mil_short
Q4
G
37,39,40,41 SUSB
*MTN7002ZHS3
S3 circuit:- DRAM_RST# to memory
should be high during S3
1.5V
R304
R306 *0_04
1K_04
Q22
MTN7002ZHS3
S D
CPUDRAMRST# R305 1K_04
DDR3_DRAMRST#
DRAMRST_CNTRL 6,21
R319 C515
4.99K_1%_04 0.047u_10V_X7R_04
6,37,40 1.5VS_CPU
6,9,10,27,37,40 1.5V
2,5,25,26,27,37 1.05VS_VTT
3.3V
3.3VS
1.05VS_VTT
9,10