Philips LC7.1E Service Manual page 77

Circuit Descriptions, Abbreviation List, and IC Data Sheets
9.5.1 Region-dependent applications
S C A R T 1
S C A R T 2
S ID E A V
O n b o a rd E X T 3
"Block diagram video processing - EU version" shows the input
and output signals to and from the Trident Video Processor in
EU applications.
During analogue reception, a CVBS signal coming from the
analogue front-end is fed to the video processor via pin
CVBS1. During digital reception, the video signal coming from
the MPEG decoder (MOJO) is fed to the video processor via
pins FS1, PC_B, PC_G and PC_R.
S ID E A V
D M M I c o n n e c to r
P C V G A
H D M I2
H D M I1
A n a lo g u e
F ro n t E n d
S C 1 _ R _ IN
S C 1 _ G _ IN
S C 1 _ B _ IN
S C 1 _ C V B S _ IN
S C 1 _ F B L _ IN
S C 2 _ Y _ C V B S _ IN
S C 2 _ C _ IN
F R O N T _ Y _ C V B S _ IN _ T
F R O N T _ C _ IN _ T
H D _ Y _ IN
H D _ P B _ IN
E X T 4
H D _ P R _ IN
IB O _ R _ IN
D i g i t a l F r o n t E n d
IB O _ G _ IN
( D V B-T
IB O _ B _ IN
d e m o d u la to r
IB O _ C V B S _ IN
a n d d e c o d e r)
H D M I_ Y (0 :7 )
H D M I_ C b (0 :7 )
H D M I2
H D M I_ C r (0 :7 )
H D M I
D e c o d e r
H D M I1
Figure 9-6 Block diagram video processing - EU version
A n a lo g u e
C V B S _ R F
F ro n t E n d
S C 2 _ Y _ C V B S _ IN
S C 2 _ C _ IN
A V 1
F R O N T _ Y _ C V B S _ IN _ T
F R O N T _ C _ IN _ T
C V I_ D T V _ S E L
IB O _ R _ IN
D M M I Y P b P r IN
IB O _ G _ IN
M U X
C V I Y P b P r
C V I1 IB O _ B _ IN
IB O _ C V B S _ IN
H D _ Y _ IN
H D _ P B _ IN
C V I2
H D _ P R _ IN
S C 1 _ R _ IN
S C 1 _ G _ IN
S C 1 _ B _ IN
P C _ V G A _ H
P C _ V G A _ V
H D M I_ Y (0 :7 )
H D M I_ C b (0 :7 )
H D M I_ C r(0 :7 )
H D M I
D e c o d e r
Figure 9-7 Block diagram video processing - AP version
C V B S _ R F
C V B S 1
P R _ R 2
Y _ G 2
P B _ B 2
P B _ B 3
F B 1
C V B S _ O U T 1
P R _ R 3
F S 2
Y _ G 3
C
T r id e n t
Video Processor
SVP CX32
Y _ G 1
P B _ B 1
C V B S _ O U T 2
P R _ R 1
P C _ R
P C _ G
P C _ B
F S 1
The video processor also interfaces the SCART1 & 2 input,
side AV, EXT4 (HD where applicable) and HDMI1 & 2 input.
Through the SCART1 & 2 connectors, a monitor output is
foreseen.
C V B S 1
P R _ R 3
F S 2
Y _ G 3
C
P C _ R
P C _ G
P C _ B
T r i d e n t
F S 1
Video Processor
Y _ G 1 SVP CX32
P B _ B 1
P R _ R 1
C V B S _ O U T 2
P R _ R 2
Y _ G 2
P B _ B 2
A IN _ H S
A IN _ V S
LC7.1E LA
C V B S
S C A R T 1 M o n ito r o u t
C V B S
S C A R T 2 M o n ito r o u t
G_16860_060.eps
310107
C V B S
C IN C H M o n ito r o u t
G_16860_061.eps
310107
9. EN 77