Nokia RM-506 Service Manual page 221

RM-505; RM-506
System Module and User Interface
Imaging Video baseband is implemented using DM5001D processor. DM5001D processor is a hardware
accelerator for Imaging and Video application. This processor controls all the cameras and flashes in the
system.
This processor is controlled by Rapido processors via SPI interface. Boot code is downloaded into DM5001D
Internal memory via the SPI interface at power on. Further application code (self-test, image capture, video
capture) is transferred depending on the usage case.
Video and still image data is passed to the Rapido for display and storage after processing over a CCP bus
(CCP_CMT).
• Primary Camera module (5 Mpixel Camera)
The camera module is SMIA95 compliant and is configured by the DM5001D using I2C control bus. Image
data is transferred to the DM5001D over a CCP balanced bus (HIRES_CCP)
• Secondary VGA Camera module
The camera module is electrically SMIA compliant module (not mechanically) and is configured by the
DM5001D using I2C control bus. Image data is transferred to the DM5001D over a CCP balanced bus
(LORES_CCP)
• Flash LED
The camera flash LED is controlled from the DM5001D via the ADP1653 driver. Driver has GPIO control for
STROBE/ENABLE and I2C bus control for configuring.
The camera subsystem is powered from 1.3V, 1.8V and 2.8V discrete regulators. The 1.3V regulator is powerd
from 1.8V regulator. The 1.8V and 2.8V regulators are powerd from VBAT. The LED driver is powered directly
from the VBAT supply. These supplies are turned off/on by the host processor using the GPIO (Julie_REG_EN),
depending on the camera usage.
The high-level camera subsystem block diagram is presented in the following figure:
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