Sony HCD-SR1 Service Manual page 115

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DMB08 BOARD IC607 CXD9618BQ (AUDIO DIGITAL SIGNAL PROCESSOR)
Pin No. Pin Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14 SCKOUT
15
16
17
18
TE
L 13942296513
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
www
40
41
42
.
43 DQM/OE0
44
45
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I/O
VSS — Ground terminal
XRST I Reset signal input from the system controller
EXTIN I Master clock signal input terminal
FS2 I Sampling frequency selection signal input terminal
VDDI — Power supply terminal (+2.6V)
FS1 I Sampling frequency selection signal input terminal
PLOCK O Internal PLL lock signal output terminal Not used
VSS — Ground terminal
MCLK1 I System clock signal input terminal (13.5 MHz)
VDDI — Power supply terminal (+2.6V)
VSS — Ground terminal
MCLK2 O System clock signal output terminal (13.5 MHz)
Master/slave selection signal input terminal
MS I
"L": slave, "H": master (fixed at "L" in this set)
O Internal system clock signal output to the D/A converter and stream processor
LRCKI1 I L/R sampling clock signal (44.1 kHz) input from the digital audio processor
VDDE — Power supply terminal (+3.3V)
BCKI1 I Bit clock signal (2.8224 MHz) input from the digital audio processor
SDI1 I Front L-ch and R-ch audio serial data input from the digital audio processor
L/R sampling clock signal (44.1 kHz) output to the D/A converter and stream
LRCKO O
processor
BCKO O Bit clock signal (2.8224 MHz) output to the D/A converter and stream processor
VSS — Ground terminal
KFSIO I Audio clock signal (11.2896 MHz) input from the digital audio processor
SDO1 O Front L-ch and R-ch audio serial data output to the stream processor
SDO2 O Center and woofer audio serial data output to the stream processor
SDO3 O Rear L-ch and R-ch audio serial data output to the stream processor
SDO4 O Audio serial data output to the D/A converter
SPDIF O S/PDIF signal output terminal
LRCKI2 I L/R sampling clock signal (44.1 kHz) input from the A/D converter
BCKI2 I Bit clock signal (2.8224 MHz) input from the A/D converter
SDI2 I Center and woofer audio serial data input from the digital audio processor
VSS — Ground terminal
HACN O Acknowledge signal output to the system controller
HDIN I Write data input from the system controller
HCLK I Clock signal input from the system controller
HDOUT O Read data output to the system controller
HCS I Chip select signal input from the system controller
SDCLK O Clock signal output terminal
CLKEN O Clock enable signal output terminal
RAS O Row address strobe signal output terminal
VDDI — Power supply terminal (+2.6V)
VSS — Ground terminal
x ao
y
CAS O Column address strobe signal output terminal
i
O Output terminal of data input/output mask
CS0 O Chip select signal output to the S-RAM
WE0 O Write enable signal output to the S-RAM
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8
Q Q
3 6 7 1 3
Not used
Not used
u163
.
HCD-SR1/SR2/SR3
2 9 9 4 2 8
Description
"L": reset
Not used
Not used
Not used
1 5 0 5 8 2 9 9 4
Not used
Not used
m
co
Not used
Not used
9 9
2 8 9 9
37