Sony HCD-FR1 Service Manual page 122

HCD-FR1/FR8/FR9
QQ
3 7 63 1515 0
Pin No. Pin Name
46 VDDE
47 WMD1
48 VSS
49 WMD0
50 PAGE2
51 VSS
52, 53 PAGE1, PAGE0
54 BOOT
55 BTACT
56 BST
57 MOD1
58 MOD0
59 EXLOCK
60 VDDI
61 VSS
62, 63 A17, A16
64 to 66 A15 to A13
TE
L 13942296513
67 GP10
68 GP9
69 GP8
70 VDDI
71 VSS
72 to 75 D15 to D12
76 VDDE
77 to 80 D11 to D8
81 VSS
82 to 85 A9, A12 to A10
86 TDO
87 TMS
88 XTRST
89 TCK
90 TDI
91 VSS
92 to 97 A8 to A3
98, 99 D7, D6
100 VDDI
101 VSS
102 to 105 D5 to D2
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106 VDDE
107, 108 D1, D0
109, 110 A2, A1
.
111 VSS
112 A0
113 PM
42
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I/O
— Power supply terminal (+3.3V)
I S-RAM wait mode setting terminal
— Ground terminal
I S-RAM wait mode setting terminal
O Page selection signal output terminal
— Ground terminal
O Page selection signal output terminal
I Boot mode control signal input terminal
O Boot mode state display signal output terminal
I Boot strap signal input from the system controller
PLL input frequency selection signal input terminal
I
"L": 384fs, "H": 256fs (fixed at "H" in this set)
Mode setting terminal
I
"L": single chip mode, "H": use prohibition (fixed at "L" in this set)
I PLL lock error and data error flag input from the digital audio interface IC
— Power supply terminal (+2.6V)
— Ground terminal
O Address signal output terminal
O Address signal output to the S-RAM
L/R sampling clock signal (44.1 kHz) output to the D/A converter and stream
O
processor
O Decode signal output to the system controller
I Bit 1 input terminal of channel status from the digital audio interface IC
— Power supply terminal (+2.6V)
— Ground terminal
I/O Two-way data bus with the S-RAM
— Power supply terminal (+3.3V)
I/O Two-way data bus with the S-RAM
— Ground terminal
O Address signal output to the S-RAM
O Simple emulation data output terminal
I Simple emulation data input start/end detection signal input terminal
I Simple emulation asychronous break input terminal
I Simple emulation clock signal input terminal
I Simple emulation data input terminal
— Ground terminal
O Address signal output to the S-RAM
I/O Two-way data bus with the S-RAM
— Power supply terminal (+2.6V)
— Ground terminal
I/O Two-way data bus with the S-RAM
— Power supply terminal (+3.3V)
I/O Two-way data bus with the S-RAM
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O Address signal output to the S-RAM
i
— Ground terminal
O Address signal output to the S-RAM
I PLL reset signal input from the system controller
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2 9
8
Description
Fixed at "H" in this set
Fixed at "H" in this set
Not used
Not used
Not used
Not used
Q Q
3 6 7 1 3 1 5
Not used
Not used
Not used
co
.
9 4 2 8
Not used
0 5 8 2 9 9 4 2 8
Not used
Not used
m
"L": reset
9 9
9 9