Sony HCD-FR1 Service Manual page 125

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Pin No. Pin Name
53
54
55
56
57
58
59, 60 HA0, HA2
61
62, 63 HCS0, HCS1
64
65
66 to 69 MDB0 to MDB3
70
71
72
73 to 75 MDB5 to MDB7
76
77
78
TE
L 13942296513
79, 80 MA0, MA1
81
82 to 87 MA2 to MA7
88
89
90
91
92
93
94
95
96, 97 MDB8, MDB9
98
99
100
101, 102 MDBB, MDBC
103
104 to 106 MDBD to MDBF
107
108
www
109
110
111
.
112
113, 114 ASF1, AFS2
115
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I/O
DVD mode: Serial data request signal input from the DVD system processor
XHAC I
SACD mode: Serial data request signal input from the DSD decoder
HINT O Not used
XS16 O Not used
HA1 I Not used
XPDI I/O Not used
VDDS — Power supply terminal (+5V) (digital system)
I Not used
VSS — Ground terminal (digital system)
I Not used
VDD — Power supply terminal (+3.3V) (digital system)
DASP I/O Not used
I/O Two-way data bus with the D-RAM
VSS — Ground terminal (digital system)
MDB4 I/O Two-way data bus with the D-RAM
VDD5V — Power supply terminal (+5V)
I/O Two-way data bus with the D-RAM
XMWR O Write enable signal output to the D-RAM
VDD — Power supply terminal (+3.3V) (digital system)
XRAS O Row address strobe signal output to the D-RAM
O Address signal output to the D-RAM
VSS — Ground terminal (digital system)
O Address signal output to the D-RAM
VDD — Power supply terminal (+3.3V) (digital system)
MA8 O Address signal output to the D-RAM
VSS — Ground terminal (digital system)
MA9 O Address signal output to the D-RAM
MNT1 O EEPROM ready signal output to the mechanism controller
Operation clock signal output for PSP physical disc mark detection to DSD
MNT2 O
decoder
XMOE O Output enable signal output to the D-RAM
XCAS O Column address strobe signal output to the D-RAM
I/O Two-way data bus with the D-RAM
VSS — Ground terminal (digital system)
MDBA I/O Two-way data bus with the D-RAM
VDD — Power supply terminal (+3.3V) (digital system)
I/O Two-way data bus with the D-RAM
VDD5V — Power supply terminal (+5V)
I/O Two-way data bus with the D-RAM
GFS O Guard frame sync signal output to the mechanism controller
VSS — Ground terminal (digital system)
APEO O Absolute phase error signal output
VDD — Power supply terminal (+3.3V) (digital system)
x ao
y
DASYO O RF binary signal output
i
GNDA5 — Ground terminal (analog system)
— Filter connected terminal for selection the constant asymmetry compensation
DASYI I Analog signal input after integrated from the RF binary signal
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HCD-FR1/FR8/FR9
2 9 9 4 2 8
Description
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