Sony BDP-CX7000ES Service Manual page 120

BDP-CX7000ES
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Pin No. Pin Name
G2 BL_VS
G3 LED_TEST2
G4 VDD15
G11 GND
G12 VDD33
G13 GND
G14 VOCK
H1 GND
H2 STEST10
H3 LED_TEST3
H4 VDD15
H11 VDD15
H12 GND
H13 VOD7
H14 VOD8
J1 TEN
J2 STEST5
J3 LED_TEST4
J4 STEST4
J11 VDD15
J12 GND
J13 VOD5
J14 VOD6
K1, K2 VIDC9, VIDC8
K3 LED_TEST5
K4 STEST3
K11 GND
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L 13942296513
K12 VDD15
K13, K14 VOD3, VOD4
L1, L2 VIDC7, VIDC6
L3 LED_TEST6
L4 VDD15
L5 GND
L6, L7 VDD15
L8 GND
L9 VDD15
L10 STEST2
L11 GND
L12 VDD15
L13, L14 VOD1, VOD2
M1, M2 VIDC5, VIDC4
M3 GND
M4 LED_TEST7
M5, M6 TMC1, TMC2
M7 VDD33
M8 GND
M9, M10 N.C
M11 GND
M12 VDD33
M13 VOVS
M14 VOD0
N1 VIDC3
N2 GND
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N3 VIDC1
VIDY9, VIDY7, VIDY5,
N4 to N8
VIDY3, VIDY1
N9 VIVS .
N10 VICK
N11 STEST1
N12 TRST
120
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I/O
I Not used
O Not used
- Power supply terminal (+1.5V)
- Ground terminal
- Power supply terminal (+3.3V)
- Ground terminal
O Video clock signal output to the FPGA and video encoder
- Ground terminal
I Not used
O Not used
- Power supply terminal (+1.5V)
- Power supply terminal (+1.5V)
- Ground terminal
O Digital video (Y) signal output to the video encoder
O Digital video signal output terminal
I Enable signal input terminal (for JTAG)
I Not used
O Not used
I Not used
- Power supply terminal (+1.5V)
- Ground terminal
O Digital video signal output terminal
O Digital video (Y) signal output to the video encoder
O Digital video (Cb/Cr) signal input from the FPGA
O Not used
I Not used
- Ground terminal
- Power supply terminal (+1.5V)
O Digital video signal output terminal
I Digital video (Cb/Cr) signal input from the FPGA
O Not used
- Power supply terminal (+1.5V)
- Ground terminal
- Power supply terminal (+1.5V)
- Ground terminal
- Power supply terminal (+1.5V)
I Not used
- Ground terminal
- Power supply terminal (+1.5V)
O Digital video signal output terminal
I Digital video (Cb/Cr) signal input from the FPGA
- Ground terminal
O Not used
I Mode control signal input terminal (for JTAG)
- Power supply terminal (+3.3V)
- Ground terminal
- Not used
- Ground terminal
- Power supply terminal (+3.3V)
O Vertical sync signal output to the FPGA and video encoder
O Digital video signal output terminal
I Digital video (Cb/Cr) signal input from the FPGA
- Ground terminal
I Digital video (Cb/Cr) signal input from the FPGA
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I Digital video (Y) signal input from the FPGA
I i Vertical sync signal input from the FPGA
I Video clock signal input from the FPGA
I Not used
I Reset signal input terminal (for JTAG) Not used
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2 9
8
Description
Not used
Not used
Not used
Q Q
3 6 7 1 3 1 5
Not used
Not used
Not used
Not used
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9 4 2 8
0 5 8 2 9 9 4 2 8
m
9 9
9 9