Uisource Signal; Figure 4-26. Update* Input Signal Timing; Figure 4-27. Update* Output Signal Timing - National Instruments VXI-MIO Series User Manual

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Rising-edge
polarity
Falling-edge
polarity

Figure 4-26. UPDATE* Input Signal Timing

Figure 4-27. UPDATE* Output Signal Timing

The DACs are updated within 100 ns of the leading edge. Separate the
UPDATE* pulses with enough time that new data can be written to the
DAC latches.
The VXI-MIO Series module UI counter normally generates the
UPDATE* signal unless you select some external source. The UI
counter is started by the WFTRIG signal and can be stopped by software
or the internal Buffer Counter.
D/A conversions generated by either an internal or external UPDATE*
signal do not occur when gated by the software command register gate.

UISOURCE Signal

Any PFI pin can externally input the UISOURCE signal, which is not
available as an output on the I/O connector. The UI counter uses the
UISOURCE signal as a clock to time the generation of the UPDATE*
signal. You must configure the PFI pin you select as the source for the
UISOURCE signal in the level-detection mode. You can configure the
t
w
t
= 10 ns minimum
w
t
w
t
= 300-350 ns
w
4-37
Chapter 4 Signal Connections
VXI-MIO Series User Manual