Yamaha AD8HR Service Manual page 16

Ad converter with remote preamp
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AD8HR
MBCG61594-130 (X3299A00) ATSC2A
PIN
NAME
I/O
NO.
1
V
DD
2
XTST
I
3
V
SS
4
WT_X
I
5
RD_X
I
6
CS_X
I
7
HS_SEL
I
8
RES_X
I
9
V
SS
10
ADD[0]
I
11
ADD[1]
I
12
ADD[2]
I
13
ADD[3]
I
14
ADD[4]
I
15
ADD[5]
I
16
ADD[6]
I
17
ADD[7]
I
18
V
DD
19
V
SS
20
DAT[0]
I/O
21
DAT[1]
I/O
22
DAT[2]
I/O
23
DAT[3]
I/O
24
V
DD
25
V
SS
26
DAT[4]
I/O
27
DAT[5]
I/O
28
DAT[6]
I/O
29
DAT[7]
I/O
30
V
SS
31
V
DD
32
PA_I_H_MODE[0]
I
33
PA_I_H_MODE[1]
I
34
PA_I_H_MODE[2]
I
35
PA_O_H_MODE[0]
I
36
PA_O_H_MODE[1]
I
37
PA_O_H_MODE[2]
I
38
PA_SI0_ATI
I
39
PA_SI1
I
40
PA_SI2
I
41
PA_SI3
I
42
PA_I_SW_SEL
I
43
PA_SYNC_WC_SI
I
44
PA_FS256_SI
I
45
V
SS
46
PA_FS256_SO
I
47
PA_SYNC_WC_SO
I
48
PA_O_SW_SEL
I
49
V
SS
50
PA_SO0
O
51
PA_SO1
O
52
PA_SO2
O
53
PA_SO3
O
54
V
DD
55
V
SS
56
PA_CLK_ATI
I
57
PA_H_M4_SEL
I
58
PA_O_MUTE
I
59
PB_SI0
I
60
PB_SI1
I
61
PB_SI2
I
62
PB_SI3
I
63
PB_I_SW_SEL
I
64
PB_SYNC_WC_SI
I
65
PB_FS256_SI
I
66
V
SS
67
PB_FS256_SO
I
68
PB_SYNC_WC_SO
I
69
PB_O_SW_SEL
I
70
PB_I_H_MODE[0]
I
71
PB_I_H_MODE[1]
I
72
PB_I_H_MODE[2]
I
16
FUNCTION
Power supply +3.3V
LSI test pin
Ground
CPU interface write input
CPU interface read input
CPU interface chip select input
Chip active select
System reset input
Ground
CPU interface address bus
Power supply +3.3V
Ground
CPU interface data bus
Power supply +3.3V
Ground
CPU interface data bus
Ground
Power supply +3.3V
Port A audio data input mode select
Port A audio data output mode select
Port A audio data input
Port A audio data input sync/wc select
Port A audio data input sync/wc input
Port A audio data input bit clock input (256fs)
Ground
Port A audio data output bit clock input (256fs)
Port A audio data output sync/wc input
Port A audio data output sync/wc select
Ground
Port A audio data output
Power supply +3.3V
Ground
Port A ADAT clock input
Port A audio data input buffer active select
Port A mute
Port B audio data input
Port B audio data input sync/wc select
Port B audio data input sync/wc input
Port B audio data input bit clock input (256fs)
Ground
Port B audio data output bit clock input (256fs)
Port B audio data output sync/wc input
Port B audio data output sync/wc select
Port B audio data input mode select
PIN
NAME
I/O
NO.
73
V
Power supply +3.3V
DD
74
PB_H_M4_SEL
I
Port B audio data input buffer active select
75
PB_O_MUTE
I
Port B mute
76
V
Ground
SS
77
PB_SO0_ATO
O
78
PB_SO1
O
Port B audio data output
79
PB_SO2
O
80
PB_SO3
O
81
V
Ground
SS
82
PB_O_H_MODE[0]
I
83
PB_O_H_MODE[1]
I
Port B audio data output mode select
84
PB_O_H_MODE[2]
I
85
PC_I_H_MODE[0]
I
86
PC_I_H_MODE[1]
I
Port C audio data input mode select
87
PC_I_H_MODE[2]
I
88
PC_H_M4_SEL
I
Port C audio data input buffer active select
89
PC_SI0_ATI
I
Port C audio data input
90
V
Power supply +3.3V
DD
91
V
Ground
SS
92
PC_SI1
I
93
PC_SI2
I
Port C audio data input
94
PC_SI3
I
95
PC_I_SW_SEL
I
Port C audio data input sync/wc select
96
PC_SYNC_WC_SI
I
Port C audio data input sync/wc input
97
PC_FS256_SI
I
Port C audio data input bit clock input (256fs)
98
V
Ground
SS
99
PC_FS256_SO
I
Port C audio data output bit clock input (256fs)
100
PC_SYNC_WC_SO
I
Port C audio data output sync/wc input
101
PC_O_SW_SEL
I
Port C audio data output sync/wc select
102
V
Ground
SS
103
PC_SO0
O
104
PC_SO1
O
Port C audio data output
105
PC_SO2
O
106
PC_SO3
O
107
V
Ground
SS
108
PC_O_MUTE
I
Port C mute
109
PC_O_H_MODE[0]
I
110
PC_O_H_MODE[1]
I
Port C audio data output mode select
111
PC_O_H_MODE[2]
I
112
PC_CLK_ATI
I
Port C ADAT clock input
113
V
Ground
SS
114
PD_I_H_MODE[0]
I
115
PD_I_H_MODE[1]
I
Port D audio data input mode select
116
PD_I_H_MODE[2]
I
117
V
Ground
SS
118
PD_H_M4_SEL
I
Port D audio data input buffer active select
119
PD_SI0
I
120
PD_SI1
I
Port D audio data input
121
PD_SI2
I
122
PD_SI3
I
123
PD_I_SW_SEL
I
Port D audio data input sync/wc select
124
PD_SYNC_WC_SI
I
Port D audio data input sync/wc input
125
PD_FS256_SI
I
Port D audio data input bit clock input (256fs)
126
V
Power supply +3.3V
DD
127
V
Ground
SS
128
PD_FS256_SO
I
Port D audio data output bit clock input (256fs)
129
PD_SYNC_WC_SO
I
Port D audio data output sync/wc input
130
PD_O_SW_SEL
I
Port D audio data output sync/wc select
131
V
Ground
SS
132
PD_SO0_ATO
O
133
PD_SO1
O
Port D audio data output
134
PD_SO2
O
135
PD_SO3
O
136
V
Ground
SS
137
PD_O_MUTE
I
Port D mute
138
V
Ground
SS
139
PD_O_H_MODE[0]
I
140
PD_O_H_MODE[1]
I
Port D audio data output mode select
141
PD_O_H_MODE[2]
I
142
XSM
I
LSI test pin
143
PA_WC_ATI
O
Port A ADAT word clock output
144
PC_WC_ATI
O
Port C ADAT word clock output
MAIN: IC921
FUNCTION

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