Marantz DR2100 Service Manual page 24

CDM V AM1250
HF amp.
Trig enta
Diode signals
Radial , focus
Motor, sledge
Figure 8-6
8.3.1 Supply Voltages
Description
The CD main board receives +5V and +12V from the CDR main
board via respectively pin 16 and pin 15 of connector 1208. The
+5V is split up into +5VHF and +5V. The +5VHF is used mainly
for the diode currents and the HF-amplifier. The +5V is used for
the digital part of the board. On the board a +3V3 is made from
the +5V for the decoder CD10 and an A3V3 for the DAC
UDA1320. The +12V is split up into A12V for the audio output
stage and +12V for the power drivers of the CDM.
Measurements
Connect following supplies to next pins :
+5V + 5% to pin 16 of connector 1208.
+12V + 5% to pin 15 of connector 1208.
Ground reference to pin 17 of connector 1208.
Keep microprocessor 7202 in reset by forcing pin 7 of
connector 1208 to +5V. Check the following voltages :
Point
Position 1000 pins 1,3
Position 7000 pins 5,17,21,57
Position 7005 pin 14
Position 7020 pins 25
Position 7020 pins 26,27,28
Position 7021 pin 5
Position 7022 pin 5
Position 7025 pin 16
Position 7202 pin 38
Position 7309 pins 4,13
Position 7120 pin 8
Figure 8-7
8.3.2 Clock Signals
Description
The microprocessor has its own Xtal or resonator of 12MHz.
The CD10 needs a clock of 8.4672MHz + 100ppm. This speed
also relates to the disc speed. To avoid locking problems
between the two drives in the CDR775, both drives run on the
same clock. Therefore the CD main board gets the clock for the
decoder from the CDR main board via pin 2 of connector 1208.
The DAC needs a system clock to drive its internal digital filters
and to clock the I2S signals from the decoder. In our case this
is 11.2896MHz (CL11) generated by the CD10.
Measurements
Connect the power supply as described above in "1.1.1.
Supply Voltages".
Loader assy
PROCESSOR
CD10
SERVO
DECODER
UDA1320
DAC
CL96532086_048.eps
Voltage
±
+5V 5%
±
+3. 3V 5%
±
+5V 5%
±
+5V 5%
±
+10 10%
±
+12V 10
±
+12V 10
±
+5V 5%
±
+5V 5% ( ot her appl. 3V3 possible)
±
+3V 3 5%
±
+12V 10
CL96532086_049.eps
Connect on pin 2 of position 1208 a clock signal of 8.4672
MHz ( 100ppm minimum rise time of 50ns and at TTL level
(0V and +5V).
Keep microprocessor 7202 in reset by forcing pin 7 at
position 1208 to +5V.
DSA
Release the reset. Now, the processor will reset the CD10
for at least 75
The output clock CL11 should be available now at pin 42 of
IIS, DOBM
the CD10.
ANA OUT
Check the following frequencies :
080999
Point
Position 7000 pin 16
Position 7202 pins 14,15
Position 7309 pin 6
Position 7309 pin 1
Position 7309 pin2
8.3.3 CD10 Decoder/Servo SAA7324 (7000)
Description
The CD10 is a single chip combining the functions of a CD
decoder, digital servo and bitstream DAC. The decoder/servo
part is based on the CD7. The decoding part supports a full
audio specification and can operate at single speed (n=1) and
double speed (n=2).
Block Diagram
D1 D2 D3 D4
8 9 10
12
R1
ADC
13
R2
V
7
ref
V
RIN
GENERATOR
40
SCL
39
SDA
MICROCONTROLLER
INTERFACE
41
RAB
42
SILD
2
HFIN
1
HFREF
FRONT
3
END
ISLICE
6
I
ref
25
TEST1
080999
31
TEST
TEST2
44
TEST3
24
SELPLL
16
CRIN
15
TIMING
CROUT
26
CL16
49
CL11/4
48
SBSY
47
SFSY
46
SUB
45
RCK
DECODER
43 MICRO-
STATUS
CONTROLLER
INTERFACE
38
RESET
24
µs.
Frequency
±
8.4672 MHz 100ppm
±
12MHz 5%
±
11.2896 MHz 100ppm
±
2.1168 MHz 100ppm
±
44.1kHz 100ppm
Figure 8-8
V V V
SSA2 DDA2 SSD2
V V V V V V
SSA1 DDA1 SSD1 SSD3 DDD1(P)
4 14 5 17 33 50 58 52
11
PRE- CONTROL
PROCESSING FUNCTION
CONTROL
PART
MOTOR
CONTROL
DIGITAL
ERROR
PLL
CORRECTOR
FLAGS
EFM
DEMODULATOR
AUDIO
PROCESSOR
INTERFACE
SRAM
INTERFACE
RAM
ADDRESSER
(LOOPBACK)
INTERFACE
SUBCODE
PROCESSOR
PEAK
DETECT
BITSTREAM
VERSATILE PINS
INTERFACE
KILL
63 34 61 62 32
V1 V2/ V4 V5 KILL
V3
Figure 8-9
CL96532086_050.eps
080999
DDD2(C)
57
54
RA
OUTPUT 55
FO
STAGES
56
SL
64
LDON
59
MOTO1
60
MOTO2
53
CFLG
EBU 51
DOBM
30
EF
29
SERIAL
SCLK
DATA
28
WCLK
27
DATA
37
SCLI
SERIAL
35
DATA
WCLI
36
SDI
20
V
neg
21
V
pos
18
DAC LN
19
LP
22
RN
23
RP
CL96532086_051.eps
080999