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8.
Faultfinding Guide
8.1
Display Board
8.1.1
Description of display board
General description
The display board has three major parts : the LCD (Liguid
Crystal Display), the display controller and the keyboard.
The display controller is controlled by the DASP master
processor on the CDR main board. The communication
protocol used is I2C. So all the information between DASP and
display controller goes via the SDA or I2C DATA and SCL or
I2C CLK lines. Communication is always initiated by the DASP
on the CDR main board. Unlike the previous generations of
CDR players, the interrupt generated by the display controller
at key-press or reception of remote control is not used. Instead,
the DASP polls the display controller for these events.
lock Diagram around µ-Com
B
MB90550A
LCD DISPLAY
LED
LED
Drive
Lines
on/stadby/timer
LCD DRV.
Control
Line
HOST
IIC Bus
DASP
Player
Type
Select
Resister
Lines
Matrix
Key Input
Each key is detected by changing the voltage level shown below.
3.5V
<4.5V
2.5V
<3.5V
KEY0 (P38)
PROGRAM
CANCEL/DELITE
KEY1(P39)
CD
CD STOP
PLAY/PAUSE
(CD SELECT)
KEY2(P40)
SOURCE
REC TYPE
KEY3(P41)
CDR
ERASE
PLAY/PAUSE
If this recorder is STANDBY state, the power will be recovered when the key is pressed.
Stop Key can be work to select either CDR or CD.
LCD
Control
Line
KEY
LCD DRV.
SW.
Keyboard
Control
Lines
Extra Key
SW.
Extra
Keyboard
Front
Control
u-COM
Lines
RC-5/SYSTEM
Bus in
Easyjog
RC-5
Control
SYSTEM
Lines
Bus in/out
SYSTEM
EASYJOG
Bus out
1.5V
<2.5V
0.5V
<1.5V
MENU/STORE
DISPLAY
DOOR OPEN
CD/CDR FF
CD/CDR REW
CD
OPEN/CLOSE
REC
CDR STOP
STAND BY
(CDR SELECT)
FINALISE
CDR
TRAY
ENTER
OPEN/CLOSE
Figure 8-1
17
Pin Configuration
P20/A16
1
P21/A17
2
P22/A18
3
P23/A19
4
P24/A20
5
P25/A21
6
P26/A22
7
P27/A23
8
P30/ALE
9
P31/RD
10
V
11
SS
P32/WRL
12
P33/WRH
13
P34/HRQ
14
P35/HAK
15
16
P36/RDY
P37/CLK
17
P40/SCK
18
P41/SOT
19
P42/SIN
20
P43/SCK1
21
P44/SOT1
22
V
23
CC
P45/SIN1
24
P46/ADTG
25
P47/SCK0
26
C
27
P50/SDA0/SOT0
28
P51/SCL0/SIN0
29
P52/SDA1
30
(FPT-100P-M06)
<0.5V
TRAY
-COM DESCRIPTION
Pin PORT
SIGNAL
I/O
1
P20/A16
LCD_DIM
O
LCD back light of DIMMER Control
2
P21/A17
LCD_BL
O
LCD backlight ON/OFF
3
P22/A18
POWER_LED
O
Power ON LED
4
P23/A19
STB_LED
O
Standby LED
5
P24/A20
SYS_SW
I
When Bus Switch
6
P25/A21
SYS_MUTE
O
SYSTEM LINE OUT OF MUTE
7
P26/A22
STB_MUTE
O
Power On < - > MUTE when STANDBY
is activate
8
P27/A23
CDR/Through
O
To switch AUDIO OUT
9
P30/ALE
N.C.
I
80
PA4/CKOT
10
P31/RD
N.C.
I
79
PA3
11
VSS
GND
78
PA2
12
P32/WRL
N.C.
I
77
RST
13
P33/WRH
N.C.
I
76
PA1/OUT3
14
P34/HRQ
N.C
I
75
PA0/OUT2
15
P35/HAK
N.C.
I
74
P97/PPG5
16
P36/RDY
POWER_ON
O
Power Control
73
P96/PPG4
17
P37/CLK
N.C.
I
72
P95/PPG3
18
P40/SCK
TCK.
I/O To connect Flash Writer
71
P94/PPG2
19
P41/SOT
SYS_OUT
O
SYSTEM Control bus OUTPUT
70
P93/PPG1
TRXD
To connect Flash Writer
69
P92/PPG0
68
P91/OUT1
20
P42/SIN
SYS_IN
I
SYSTEM Control bus or IR/RC5 Input
67
P92/OUT0
TTXD
To connect Flash Writer
66
P87/IN3
21
P43/SCK1
N.C.
I
65
P86/IN2
22
P44/SOT1
N.C.
I
64
P85/IN1
23
VCC
+5STB
--
VCC
63
P84/IN0
24
P45/SIN1
N.C.
I
62
P83/TOT1
25
P46/ADTG
N.C.
I
61
P82/TOT0
26
P47/SCK0
N.C.
I
60
P81/TIN1
27
C
C
59
P80/TIN0
28
P50/SDA0/SOT0 ROM_SDA
I/O SERIAL DATA to EEPROM
58
P77/IRQ7
29
P51/SOL0/SIN0
ROM_SCL
O
SERIAL DATA to EEPROM
57
P76/IRQ6
56
P75/IRQ5
30
P52/SDA1
IIC_DATA
I/O DATA Communication to CDR Module
55
P74/IRQ4
IIC Interface
54
P73/IRQ3
31
P53/SCL1
IIC_CLK
I/O CLK Communication to CDR Module
53
P72/IRQ2
IIC Interface
52
HST
32
P54/SDA2
N.C.
I
51
MD2
33
P55/SCL2
N.C.
I
34
AVCC
+5STB
--
VCC
35
AVRH
+5STB
--
VCC
36
AVRL
GND
37
AVSS
GND
38
P60/AN0
KEY_IN_0
I
KEY_0 INPUT
39
P61/AN1
KEY_IN_1
I
KEY_1 INPUT
40
P62/AN2
KEY_IN_2
I
KEY_2 INPUT
41
P63/AN3
KEY_IN_3
I
KEY_3 INPUT
42
VSS
GND
43
P64/AN4
N.C.
I
44
P65/AN5
N.C.
I
45
P66/AN6
N.C.
I
46
P67/AN7
N.C.
I
47
P70/IRQ0
LT1
I
RESET signal from CDR
48
P71/IRQ1
N.C.
I
49
MD0
TMODE
I
To changing CPU Mode
50
MD1
MD1
I
To changing CPU Mode
51
MD2
TAUX3
I
To changing CPU Mode
52
HST
HST
I
STANDBY input signal by hardware
53
P72/IRQ2
D_MOTOR_REV
O
Door REV
Motor ON
54
P73/IRQ3
D_MOTOR_FWD
O
Door FWD
Motor ON
55
P74/IRQ4
D_OPEN_SW
I
Door Open
56
P75/IRQ5
D_CLOSE_SW
I
Door Close
57
P76/IRQ6
JOG_A
I
JOG A
58
P77/IRQ7
JOG_B
I
JOG B
59
P80/TIN0
INT.
I
INTERRUPT signal from CDR Module
60
P81/TIN1
N.C.
I
61
P82/TOT0
N.C.
I
62
P83/TOT1
N.C.
I
63
P84/IN0
IR_IN
I
Control bus INPUT either IR/RC5 or
SYSTEM
64
P85/IN1
IN_SW
I
CDR, CD trey hardware SW.
65
P86/IN2
CDR_IN
I
CDR Trey IN
66
P87/IN3
CD_IN
I
CD Trey IN
67
P90/OUT0
N.C.
I
68
P91/OUT1
N.C.
I
69
P92/PPG0
N.C.
I
70
P93/PPG1
N.C.
I
71
P94/PPG2
N.C.
I
72
P95/PPG3
N.C.
I
73
P96/PPG4
N.C.
I
74
P97/PPG5
N.C.
I
75
PA0/OUT2
N.C.
I
76
PA1/OUT3
N.C.
I
77
RST
CPU_RST
I
CPU RESET signal
78
PA2
N.C.
I
79
PA3
N.C.
I
80
PA4/CKOT
N.C.
I
81
VSS
GND
82
X0
8MHz X'tal
83
X1
8MHz X'tal
84
VCC
+5STB
--
VCC
85
P00/AD00
TAUX
I
To Flash Writer
86
P01/AD01
---
I
To change CPU mode
87
P02/AD02
RST
O
LCD Driver RESET
88
P03/AD03
LCD_/WR
O
WR OUTPUT to LCD Driver
89
P04/AD04
LCD_/RD
O
RD OUTPUT to LCD Driver
90
P05/AD05
A0
O
LCD Driver mode
91
P06/AD06
N.C.
I
92
P07/AD07
N.C.
I
93
P10/AD08
D0
I/O To LCD Driver
94
P11/AD09
D1
I/O To LCD Driver
95
P12/AD10
D2
I/O To LCD Driver
96
P13/AD11
D3
I/O To LCD Driver
97
P14/AD12
D4
I/O To LCD Driver
98
P15/AD13
D5
I/O To LCD Driver
99
P16/AD14
D6
I/O To LCD Driver
100 P17/AD15
D7
I/O To LCD Driver
Dimmer Control
The
-controller, MB90F553A/MB90553A adjust the brightness of LCD back light by receiving
signal from IR or SYSTEM BUS.
Mode
LCD_DIM (1Pin)
Backlight OFF
Low
Backlight ON
Low
Dimmer ON
High
18
DESCRIPTION
See DIMMER Control
See DIMMER Control
Active H
Active H
SYSTEM bus = H
Active H
Active H
DR; H, Through; L
Power ON; H
Active H
PULL UP
PULL UP
PULL DOWN
PULL UP
Active H
Active H
Active L
Active L
Active : H / Passive : L
Active L
Active L
Low (PULL UP)
PULL UP
Active L
Active L
Active L
See NJU6450 Data Sheet
Active L
Active L
Active L
See NJU6450 Data Sheet
LCD_BL (2Pin)
Low
High
Low
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