Sanyo DCS-AVD8501 Service Manual page 55

IC BLOCK DIAGRAM & DESCRIPTION
IC861 PCM1602Y (Digital to Analog Converter)
PIN ASSIGNMENTS
PIN NAME I/O
1 ZERO1/GPO1 O
2 ZERO2/PGO2 O
3 ZERO3/PGO3 O
4 ZERO4/PGO4 O
5 ZERO5/PGO5 O
6 ZERO6/PGO6 O
7 NC
8 NC
9 V 6 O
OUT
10 V 5 O
OUT
11 V 4 O
OUT
12 V 3 O
OUT
13 V 2 O
OUT
14 V 1 O
OUT
15 V O
COM
16 NC O
17 AGND5
18 V 5
CC
19 AGND6
20 NC
21 AGND4
22 V 4
CC
23 AGND3
24 V 3
CC
25 AGND2
26 V 2
CC
27 AGND1
28 V 1
CC
29 NC
30 NC
31 NC
32 NC
33 MDO O
34 MDI
35 MC
36 ML
37 RST
38 SCKI
39 SCKO O
40 BCK
41 LRCK
42 TEST
43 V
DD
44 DGND
45 DATA1
46 DATA2
47 DATA3
48 ZEROA O
NOTES: (1) Schmitt-Trigger input with internal pull-down, 5V tolerant. (2) Schmitt-Trigger inout, 5V tolerant. (3) Tri-state output.
DESCRIPTION
Zero Data Flag for V 1. Can also be used as GPO pin.
OUT
Zero Data Flag for V 2. Can also be used as GPO pin.
OUT
Zero Data Flag for V 3. Can also be used as GPO pin.
OUT
Zero Data Flag for V 4. Can also be used as GPO pin.
OUT
Zero Data Flag for V 5. Can also be used as PGO pin.
OUT
Zero Data Flag for V 6. Can also be used as PGO pin.
OUT
- No Connection
- No Connection
Voltage Output of Audio Signal Corresponding to Rch on DATA3. Up to 96kHz.
Voltage Output of Audio Signal Corresponding to Lch on DATA3. Up to 96kHz.
Voltage Output of Audio Signal Corresponding to Rch on DAYA2. Up to 96kHz.
Voltage Output of Audio Signal Corresponding to Lch on DATA2. Up to 96kHz.
Voltage Output of Audio Signal Corresponding to Rch on DATA1. Up to 192kHz.
Voltage Output of Audio Signal Corresponding to Lch on DATA1. Up to 192kHz.
Common Voltage Output. This pin should be bypassed with a 10 F capacitor to AGND.
No Connection
- Analog Ground
- Analog Power Supply, +5V
Analog Ground
-
No Connection
-
- Analog Ground
- Analog Power Supply, +5V
- Analog Ground
- Analog Power Supply, +5V
- Analog Ground
- Analog Power Supply, +5V
- Analog Ground
- Analog Power Supply, +5V
- No Connection
- No Connection
- No Connection
- No Connection
Serial Data Output for Serial Control Port
I Serial Data Input for Serial Control Port
I Shift Clock for Serial Control Port
I Latch Enable for Serial Control Port
(1)
I System Reset, Active LOW
I System Clock Inout. Input frequency is 128,192,256,384,512, or 768f
Buffered Clock Output. Output frequency is 128,192,256,384,512, or 768f
I Shift Clock Input for Serial Audio Data. Clock must be 32,48, or 64f
I Left and Right Clock Input. This clock is equal to the sampling rate, f
- Test Pin. This pin should be connected to DGND.
- Digital Power Supply, +3.3V
- Digital Ground
I Serial Audio Data Input for V
OUT
I Serial Audio Data Input for V
OUT
I Serial Audio Data Input for V
OUT
Zero Data Flag. Logical "AND" of ZERO1 through ZERO6.
(3)
(1)
(1)
(1)
(1)
(2)
1 and V 2
OUT
3 and V 4 (2)
OUT
(2)
5 and V 6
OUT
- 70 -
(2)
.
s
, or one-half of 128,192,256,384,512, or 768f
s
. (2)
s
(2)
.
s
.
s