Sanyo DCS-AVD8501 Service Manual page 53

IC BLOCK DIAGRAM & DESCRIPTION
IC813 74VHC157MTC,TC74VHC157FT
(Quad 2-Channel Multiplexer)
1 16 V
SELECT
S
2 G 15
1A A ST
1B 3 A 14 4A
B
1Y 4 13 4B
Y B
2A 5 A Y 12 4Y
2B 6 B A 11 3A
2Y 7 B 10 3B
Y
Y
8 9 3Y
GND
IC815 24LC16BT, S524L50X51 (16K EEPROM)
IC842,862~864KIA4558F, NJM4558M
(Operational Amplifier)
A OUTPUT
1
A
A -INPUT
2
A +INPUT
3
VEE(-)
4
IC816 74VHCT244,TC74VHCT244
(AFT Non-Inverted, 3-state Output)
1G
1
1A1 2
2Y4 3
1A2 4
2Y3
5
1A3 6
2Y2
7
1A4 8
9
2Y1
GND 10
CC
INPUTS
A
ST SELECT D
X
H X X
L L L
X
L L X X
L H X L
L H H H
X : Don't Care
Name Function
V Ground
SS
SDA Serial Address/Data I/O
SCL Serial Clock
WP Write Protect Input
V +2.5V to 5.5V Power Supply
CC
A0,A1,A2 No Internal Connection
8 VCC(+)
7 B OUTPUT
B
6
B -INPUT
B +INPUT
5
20 V
CC
2G
19
1Y1
18
2A4
17
1Y2
16
2A3
15
1Y3
14
13 2A2
12
1Y4
11 2A1
IC817 PCM1748(D/A Converter)
PIN CONFIGURATION
BCK 1 16
OUTPUTS DATA 2 15
LRCK 3 14
L
DGND 4 13
PCM1748
L
V 5 12
DD
H
V 6 11
CC
L
V L 7 10
OUT
H
V R 8 9
OUT
BLOCK DIAGRAM
BCK 1
Serial
LRCK 3 Input
I/F
DATA
2
ML 15
Function
MC 14
Control
I/F
MD 13
System Clock
System Clock
SCK 16
Manager
IC818 74VHC374,TCVHC374 (Octal D-type Flip Flop)
Logic Diagram
D
0
3
11
CP
CP D CP
O Q
OE 1
2
O
0
Pin Descriptions
Pin Names
D -D Data Inputs
0 7
CP Clock Pulse Input 3-STATE
OE Output Enable Input 3-STATE
O -O Outputs
0 7
IC819 NC7SZ08P5,TC7SH08FU (2 Input and Gate)
IN B
IN A
GND
- 68 -
PIN ASSIGNMENTS
PIN NAME TYPE FUNCTION
1 BCK IN Audio Data Bit Clock Input.
2 DATA IN Audio Data Bigital Input.
3 LRCK IN L-Channel and R-Channel Audio Data Latch
SCK
Enable Input.
4 DGND - Digital Ground.
ML
5 V - Digital Power Supply, +3.3V.
DD
MC
6 V - Analog Power Supply, +5V.
CC
7 V L OUT Analog Output for L-Channel.
MD OUT
8 V R OUT Analpg Output for R-Channel.
OUT
ZEROL/NA
9 AGND - Analog Ground.
ZEROR/ZEROA
10 V - Common Voltage Decoupling.
COM
11 ZEROR/ OUT Zero Flag Output for R-Channel/Zero Flag
C
COM
ZEROA Output for L/R-Channel.
AGND
12 ZEROL/NA OUT Zero Flag Output for L-Channel/No Assign.
13 MD IN Mode Control Data Input.
14 MC IN Mode Control Clock Input.
15 ML IN Mode Control Latch Input.
16 SCK IN System Clock Input.
NOTES: (1)Schmitt-trigger input, 5V tolerant. (2)Schmitt-trigger with internal
pull-down, 5V tolerant.
Output Amp and
DAC
8x
Enhanced
Oversampling
Multi level
Digital Filter
Delta-Sigma
with
Modulator
Function
Controller
Output Amp and
DAC
Zero Detect Power Supply
12 11 5 4
D D D D
1 2 3 4
4 7 8 13
D CP D CP D CP D CP
O Q O Q O Q O Q O
5 6 9 12 15
O O O O O
1 2 3 4
Truth Table
Description
Dn
H
L
X
H = HIGH Voltege Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
= LOW-to-HIGH Transition
V
1
5 CC
2
OUT Y
3 4
(1)
(1)
(1)
(2)
(2)
(2)
7 V L
OUT
Low-Pass Filter
10 V
COM
Low-Pass Filter
8 V R
OUT
6 9
D D D
5 6 7
14 17 18
D CP D CP D
Q O Q O Q
16 19
O O
5 6 7
Inputs Outputs
CP OE On
L H
L L
X H Z