Table of Contents
Advertisement
A
B
C
SCHEMATIC DIAGRAMS
DSP 1/3
1
DSP
2
3
4
5
6
7
8
9
10
D
E
F
5.0
0.1
0
0
0
0
MAIN MICROPROCESSOR
0
0
0
0
0
0
0
0
0
2.7
2.0
0.4
5.0
1.0
5.2
5.2
0
4.3
5.0
5.0
5.0
5.0
5.2
5.2
5.0
10.1
5.8
0
5.8
4.3
5.2
5.8
4.9
0.1
5.1
0.1
4.9
0
G
H
I
POINT A-1 Pin 18 of IC2
0
0.1
0
4.8
5.0
5.0
5.0
4.9
0.1
5.0
5.0
4.9
4.9
0
0
5.9
0
4.9
4.9
0
0
0
5.0
0.1
A-1
0
0
0
0
0.1
5.0
0.1
5.0
5.0
0.1
5.0
5.0
Page 108
C7
B model
to DAB_W1
J
K
L
POINT B-2 1 / Pin7, 2 / Pin8 of CB3
POWER ON
(connect the power cable)
5.0
-11.9
4.9
5.0
5.0
4.3
5.0
-11.9
4.9
5.0
-11.9
4.9
5.0
5.0
4.3
0
0.2
5.0
5.0
3.3
4.9
0
0
3.3
3.3
IC2 : M30627FJPGP
Single chip 16-bit microcomputer
8
8
Port P0
Port P1
Internal peripheral functions
Timer (16 bit)
Output (timer A): 5
Input (timer B): 6
Three-phase motor
control circuit
Watchdog timer
(15 bits)
DMAC
(2 channels)
D/A converter
(8 bit x 2 channels)
<VCC1 ports>
Port P11
Port P14
8
2
# All voltages are measured with a 10MΩ/V DC electronic volt meter.
# Components having special characteristics are marked s and must be replaced
with parts having specifications equal to those originally installed.
# Schematic diagram is subject to change without notice.
M
N
RX-N600/RX-N600D/HTR-N5060/DSP-N600
IC1 : RH5RE58AA-T1-FA
Voltage regulator
V
IN
V
OUT
2
3
+
–
Vref
1
GND
IC4 : SN74AHCT1G32DCKR
Single 2-input positive-OR gate
A
1
5
Vcc
B
2
GND
3
4
Y
8
8
8
8
8
Port P2
Port P3
Port P4
Port P5
Port P6
<VCC2 ports>
<VCC1 ports>
D/A converter
System clock
(10 bit x 8 channels
generation circuit
Expandable up to 26 channels)
XIN-XOUT
UART or
XCIN-XCOUT
clock synchronous serial I/O
PLL frequency synthesizer
(8 bit x 8 channels)
On-chip oscillator
Watchdog timer
Clock synchronous serial I/O
(Polynomial: X
16
+X
12
+X
5
+1)
(8 bit x 2 channels)
M16C/60 series 16-bit CPU core
Memory
ROM
R0H
R0L
SB
512K
R1H
R1L
USP
R2
ISP
R3
RAM
INTB
31K
A0
PC
A1
FLG
FB
Multiplier
<VCC2 ports>
Port P12
Port P13
8
8
97
Hide quick links:
Advertisement
Table of Contents
