Schematic Diagrams - Yamaha R-S300 Service Manual

A B C

SCHEMATIC DIAGRAMS

FUNCTION 1/2
1
POINT C XL401 (Pin 14 of IC402)
2
3
4
PB
TAPE
REC
5
PB
0
0
0
0
1
0
6 0
LINE
0
0
0
REC
0
0
0
0
0
0
0
0
0
0
0
2
7
8
FUNCTION (2)
IC501, 507: RP130Q501D-TR-F
Voltage regulator
IC503: LE24C023M-TLM-E
Two wire serial interface EEPROM
V DD 4 3 V OUT
9
WP
SCL
Vref
Current Limit
CE 1 2 GND
Pin No. Symbol Description
1 CE Chip Enable ("H" Active)
SDA
2 GND Ground Pin
3 V OUT Output Pin
10
4 V Input Pin
DD
★ All voltages are measured with a 10MΩ/V DC electronic voltmeter.
★ Components having special characteristics are marked
and must be replaced
with parts having specifications equal to those originally installed.
★ Schematic diagram is subject to change without notice.
D E F
CB403 to AM/FM TUNER
(G model)
C
IC402
4.5 9.6 9.6 15.7
5.2 10.1
9.6
2.5
4.5
1.9
5.3 10.1
0
0 0
0
0
0
5.0
0.3
5.0
0
5.0
5.0
0.2
0.2
0
0
0
CD IN
0
0
0
0
0
IC401 0
0
15.7
0 -15.6
0
-15.6
0
0
0
0
0
0
0
0
7.3
0
7.3 15.6
0
7.9
0
0
0
-7.8
-7.2 -15.4
VOL OUT
IC502: R5F364AENFA
Single chip 16-bit microprocessor
Page 57 B4
8 8 8
to OPERATION (2)_CB801
Port P0 Port P1 Port P1
VCC2 ports
Internal peripheral functions
Write controller High voltage generator
Timer (16-bit)
Outputs (timer A): 5
Inputs (timer B): 6
Three-phase motor control circuit
EEPROM Array
Real-time clock
PWM function (8-bit x 2)
Remote control signal
NC 1 8 VDD
receiver
(2 circuits)
Y decoder and Sense AMP
NC 2 7 WP
Watchdog timer
NC 3 6
SCL (15-bit)
Serial-Parallel converter
GND 4 5 SDA
A/D converter
(10-bit resolution X 26 channels)
D/A converter
(8-bit resolution X 2 circuits)
VCC1 ports
Port P10 Port P9 Port P8
8 8 8
G H
Page 57 B5 Page 57 B9
to OPERATION (2)_W801 to OPERATION (1)_CB701
IC501 IC507
5.6 5.0 5.6 5.0
5.6 0 5.1 0
0
0
5.0
4.6
0
1.0
0
CB404 CB504
0 5.0 MICROPROCESSOR
5.0
0
0
1.8
5.0
0.3 0
5.0 0
0 0
1.1
5.0
5.0
5.0
5.0
0.2
0.2 0
1
0 0
B
5.0
5.0
0
CB405 CB502
15.7 15.7
15.7
-15.6
-15.6
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0
0 5.1
0 0
5.1
0
-15.5
0 0
5.1
5.1
-15.5
Page 56 G6 Page 56 G3
8 8 8
to FUNCTION (3)_CB602 to FUNCTION (3)_CB601
(U, C, A models)
Port P3 Port P4 Port P5
UART or System clock generator
clock synchronous serial I/O
X IN -X OUT
(6 channels)
X CIN -X COUT
PLL frequency synthesizer
Clock synchronous serial I/O
On-chip oscillator (125 kHz)
(8 bit x 2 channels)
DMAC (4 channels)
Multi-master I 2 C-bus interface POINT A XL501 (Pin 13 of IC502)
(1 channel)
CRC arithmetic circuit
(CRC-CCITT or CRC-16)
CEC function Voltage detecter
Power-on reset
On-chip debugger
M16C/60 series
Memory
Microprocessor core
ROM IC502
SB
R0H R0L
(+5M)
R1H R1L RAM
USP
R2
ISP
R3
INTB
A0
PC IC502
A1 A1
FB FB FLG
Multiplier
(N_RST)
Port P7 Port P6
(Connect the power cable)
8 8
I J K
Page 57 I8
to OPERATION (5)_W705
CB513
5.0
0
5.0
0
W504
0
5.0
CB506
1.8
0
5.0
5.0
0
1.0
0
4.6
0
0 5.0
0
5.0
-15.5
5.0
-15.2
5.1
0
0
0.3
IC502
5.0
0
0
0
0
CB508
5.5
0
2
0
1.0
0
A 0
0
0
0 5.0
4.9
5.0
5.0
5.0
5.0
5.0
0
0
5.1
CB509
0
0 0
0
5.1 0
0
0
0
0
5.0
0
5.0
IC503
0
5.1
5.1
0
5.1
FUNCTION (1)
Page 60 F10 Page 58 G8 Page 58 G4
to DOCK_CB302 to OPERATION (12)_CB2 to OPERATION (13)_CB14
POINT B 1 / IC502 (99 pin, +5M), 2 / IC502 (12 pin, N_RST)
INRA/RECR1
INLA/RECL1
INRB/RECR2
1 IC502 1
(+5M) INLB/RECL2
INR10/RECR4
INR10/RECL4
2 IC502 2
INR11/RECR5
(N_RST)
AC POWER ON AC POWER OFF AC POWER ON
(Disconnect the power cable) (Connect the power cable)
L M N
R-S300
IC402: LC72725KM-UY-TLM-E
RDS signal demodulation IC
+3V VREF FLOUT CIN +3V
Vdda
Vddd
CLOCK
PLL
RECOVERY
REFERENCE (57kHz)
(1187.5Hz)
VOLTAGE
Vssa Vssd
VREF
57kHz
BPF
MPXIN ANTIALIASING SMOOTHING DATA RDDA
(SCF) DECODER
FILTER FILTER
RDCL
RDS-ID/READY 1 16 RDCL
RDDA 2 15 RST
RAM
MODE
(128bits) VREF 3 14 XOUT
MPXIN 4 13 XIN
RST
CLK(4.332MHz)
Vdda 5 12 Vddd
RDS-ID RDS-ID/
TEST TEST Vssa 6 11 Vssd
OSC DETECT READY
7
FLOUT 10 MODE
CIN 8
9 TEST
XIN XOUT
Page 57 J5
to OPERATION (7)_W851
Page 59 J10
to MAIN (1)_W102
Page 60 I3
to DOCK_CB303
Writing port
IC401: R2A15220FP
8-channel electronic volume with 11 input selector and tone control
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31
MUTE 51 30 TRER
MCU
AVEE
AVCC
I/F BASSR2
A VEE 52 29
53 28 BASSR1
ADCL
0/-6/-12/-18dB
ATT
ADCR 54 27 TREL
SUB2
AGND BASSL2
55 26
MAIN
INR1 56 25 BASSL1
Bass/Treble
0~-95dB,
-14~+14dB +42~0dB
-∞ (0.5dBstep)
INL1 (2dBstep) FRC
57 (0.5dBstep) Bypass 24
Tone
INR2
58 Tone+MIX 23 FR Pre-OUT
Tone
SUB
INL2 +42~0dB
59 22 FROUT
(0.5dBstep)
Tone+MIX
INR3 60 Tone Tone 21 AGND
Bypass
FLOUT
INL3 61 20
0~95dB, Bass/Treble
-∞ -14~+14dB
INR4 (0.5dBstep) (2dBstep) FL Pre-OUT
62 19
INL4 63 18 FLC
+42~-95dB
-(0.5dBstep)
INR5 64 17 CC
INL5 65 16 COUT
+42~-95dB
AGND
INR6 66 -∞(0.5dBstep) 15
+42~-95dB
-∞(0.5dBstep)
INL6 67 14 SWOUT
SWC
INR7 68 13
INL7 69 +42~-95dB 12 SRC
-∞(0.5dBstep)
70
INR8 11 SR Pre-OUT
REC
SROUT
INL8 71 10
+42~-95dB
-∞(0.5dBstep)
72 9 A GND
73 8 SLOUT
INR9 74 7 SL Pre-OUT
+42~-95dB
-∞(0.5dBstep)
INL9
75 6 SLC
76 5
AGND
77 4 SBRC
78 3 SBR Pre-OUT
79 2 SBR OUT
AGND
80 1
81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
55