Pioneer CDJ-1000MK2 Service Manual page 83

5
• Action of the CPU
t1
Measurement about 2.5 ms
After checking that /INT is L, the CPU sets /PROGRAM to H.
The FPGA checks that /PROGRAM is L, and sets /INIT and DONE
to L.
Measurement approx. 2.5 µs
t2
The CPU waits until /INT becomes H.
The FPGA checks that /PROGRAM is H, and clears the
Configuration memory, changes /INT to open drain output, and
confirms that /INT is H.
Measurement approx. 20 µs
t3
The CPU waits for several dozens of microseconds.
The FPGA confirms that /INT is H, then checks the Mode pins (M0-
M2).
t4
The CPU waits either until DONE becomes H or /INIT becomes L.
When DONE becomes H, it is judged as completion of download-
ing.
If /INT becomes L, it is judged that the downloading failed, and the
retrial starts.
If /INT becomes H and DONE becomes L, this status is temporarily
stored in the stack.
→ The program has been changed to execute retries. According to
the specifications, as /INT becomes H while the serial CLK is
input, waiting is not required. (See the waveform examples.)
If DONE does not become H even after approx. 6 ms of waiting, the
sequence is retried from the beginning up to three times.If it fails, a
timeout error is generated, and an error message is displayed.
t5
Measurement approx. 1.3 ms
If DONE becomes H, XFRST is set to H in 1 ms.
Clearance of the FPGA register and initialization.
DONE
CLK
DATA
DONE
CLK
DATA
5
6
t6
Measurement approx. 5.7 ms
XSRST is set to H 5 ms after XFRST is set to H.
Resetting the software programs of the mechanism-controller and
display controller to the defaults
t7
Measurement approx. 600 ms
XSS2 is set to L approx. 500 ms after XSRST is set to H.
After the initially downloaded program is sent to DSP2, XSS2
becomes H. Then, XSS1 is set to L to send the initially downloaded
program to DSP1. After completion, XSS1 becomes H.
t8
DGP2 is checked (timeout: 6 ms).
Transmission of the DSP program is performed in two steps. At the
first step, only the program for port initialization is transmitted, and
at the second step, the main program is sent.
First downloading
In a case when the DGP2 pin does not become L within 6 ms after
the first data transmission is completed
It is judged that downloading failed, and retries start.
* If the flag (HACK) indicating that downloading is OK from DSP2
becomes L and if downloading is OK for DSP1 itself, DSP1 sends
L to the CPU as an OK flag (DGP2).
Second downloading
In a case when the DGP2 pin does not become H within 6 ms after
the second data transmission is completed
It is judged that downloading failed, and retries start.
* If the flag (SDO4_1) indicating that downloading is OK from DSP2
becomes H and if downloading is OK for DSP1 itself, DSP1 sends
H to the CPU as an OK flag (DGP2).
CDJ-1000MK2
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