Advanced Chipset Features - DFI CA34-SC User Manual

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3.1.3 Advanced Chipset Features

Bank 0/1 DRAM Timing
Bank 2/3 DRAM Timing
SDRAM Cycle Length
DRAM Clock
Memory Hole
P2C/C2P Concurrency
Fast R-W Turn Around
System BIOS Cacheable
Video RAM Cacheable
AGP Aperture Size
AGP-4X Mode
AGP Driving Control
X
AGP Driving Value
AGP Fast Write
OnChip USB
USB Keyboard Support
OnChip Sound
OnChip Modem
CPU to PCI Write Buffer
PCI Dynamic Bursting
PCI Master 0 WS Write
↑↓→← Move
PCI Delay Transaction
PCI#2 Access #1 Retry
AGP Master 1 WS Write
AGP Master 1 WS Read
Memory Parity/ECC Check
be altered unless necessary.
Bank 0/1 DRAM Timing and Bank 2/3 DRAM Timing
CMOS Setup Utility - Copyright (C) 1984-2000 Award Software
Advanced Chipset Features
SDRAM 8/10ns
SDRAM 8/10ns
3
HCLK-33M
Disabled
Enabled
Disabled
Disabled
Disabled
64M
Enabled
Auto
DA
Disabled
Enabled
Disabled
Auto
Auto
Enabled
Enabled
Enabled
Enabled
Enter:Select
+/-/PU/PD:Value F10:Save
Enabled
F5:Previous Values
F6:Fail-Safe Defaults
Disabled
Disabled
Disabled
Award BIOS Setup Utility
Item Help
Menu Level
ESC:Exit
F1:General Help
F7:Optimized Defaults
These items should not
3

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