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3.1.3 Advanced Chipset Features
DRAM Timing Selectable
X
CAS Latency Time
X
Active to Precharge Delay
X
DRAM RAS# to CAS# Delay
X
DRAM RAS# Precharge
DRAM Read Thermal Mgmt
Buffer Strength Control
System BIOS Cacheable
Video BIOS Cacheable
Delayed Transaction
Delay Prior to Thermal
AGP Aperture Size (MB)
AGP 4X Mode
↑↓→← Move
The settings on the screen are for reference only. Your version may not be
identical to this one.
This section gives you functions to configure the system based on
the specific features of the chipset. The chipset manages bus speeds
and access to system memory resources.
be altered unless necessary.
because they provide the best operating conditions for your system.
The only time you might consider making any changes would be if
you discovered some incompatibility or that data was being lost
while using your system.
3.1.3.1 DRAM Timing Selectable
This field is used to select the timing of the DRAM.
By SPD
Phoenix - AwardBIOS CMOS Setup Utility
Advanced Chipset Features
By SPD
3
7
3
3
Disabled
Press Enter
Disabled
Disabled
Enabled
16 Min
64
Enabled
Enter:Select
+/-/PU/PD:Value F10:Save
F5:Previous Values
F6:Fail-Safe Defaults
The default settings have been chosen
The EEPROM on a DIMM has SPD (Serial Presence
Detect) data structure that stores information about
the module such as the memory type, memory size,
memory speed, etc. When this option is selected,
the system will run according to the information in
the EEPROM. This option is the default setting
because it provides the most stable condition for
the system. The "CAS Latency Time" to "DRAM
RAS# Precharge" fields will show the default settings
by SPD.
Award BIOS Setup Utility
Item Help
Menu Level
ESC:Exit
F1:General Help
F7:Optimized Defaults
These items should not
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