Advanced Chipset Features - DFI GIC68-D User Manual

3.1.3 Advanced Chipset Features

SDRAM CAS Latency Time
SDRAM Cycle Time Tras/Trc
SDRAM RAS-to-CAS Delay
SDRAM RAS Precharge Time
System BIOS Cacheable
Video BIOS Cacheable
Delayed Transaction
AGP 4X Mode
System Memory Frequency
Onboard Video
↑↓→← Move
The settings on the screen are for reference only. Your version may not be
identical to this one.
This section gives you functions to configure the system based on
the specific features of the chipset. The chipset manages bus speeds
and access to system memory resources.
be altered unless necessary.
because they provide the best operating conditions for your system.
The only time you might consider making any changes would be if
you discovered some incompatibility or that data was being lost
while using your system.
SDRAM CAS Latency Time
The default setting is 3 which is 3 clock cycles for the CAS latency.
SDRAM Cycle Time Tras/Trc
This field selects the number of SCLKs for an access cycle. The
default is 7/9.
SDRAM RAS-to-CAS Delay
This field allows you to insert a timing delay between the CAS and
RAS strobe signals, used when DRAM is written to, read from, or
refreshed. This field applies only when synchronous DRAM is installed
in the system.
CMOS Setup Utility - Copyright (C) 1984-2000 Award Software
Advanced Chipset Features
3
7/9
3
3
Disabled
Disabled
Enabled
Enabled
Auto
Enabled
Enter:Select +/-/PU/PD:Value
F5:Previous Values F6:Fail-Safe Defaults
The default settings have been chosen
Award BIOS Setup Utility
Item Help
Menu Level
F10:Save ESC:Exit F1:General Help
F7:Optimized Defaults
These items should not
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