Sony HCD-V808 Service Manual page 29

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• VIDEO BOARD IC701 HD6433032SK12F (CD MECHANISM CONTROLLER)
Pin No. Pin Name
1 CMD0
2 CMD1
3 CMD2
4 CMD3
5 SACK
6 QINT
7 VDAC-XLAT
8 DF-XLAT
9 P90/TXD
10 SUBQ
11 SQCK
12 VSS
13
14
15
16
17
18
19
20
TE
21 VCC
L 13942296513
22
23
24
25
26
27
28
29
30 VSS
31
32
33 A10
34 A11
35 A12
36 A13
37 A14
38 A15
39 A16
40 A17
41 A18
www
42 A19
43 WAIT
44 MD0
.
45 MD1
46
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I/O
I/O
I/O
Two-way data bus with the IIC interface controller (IC901)
I/O
I/O
O
Data acknowledge output to the IIC interface controller (IC901)
O
Interrupt status output to the IIC interface controller (IC901)
O Serial data latch pulse output to the video D/A converter (IC401)
O
Serial data latch pulse output to the D/A converter/digital filter (IC101)
O
Transmit data output terminal Not used (open)
I
Sub-code Q data signal input from the CXD2545Q (IC101)
O Sub-code Q data transfer clock signal output to the CXD2545Q (IC101)
—
Ground terminal
D0 I/O
D1 I/O
D2 I/O
D3 I/O
Two-way data bus with the S-RAM (IC751)
D4 I/O
D5 I/O
D6 I/O
D7 I/O
—
Power supply terminal (+5V)
A0 O
A1 O
Address signal output to the MPEG audio/video decoder (IC201) and S-RAM (IC751)
A2 O
A3 O
A4 O
A5 O
Address signal output to the S-RAM (IC751)
A6 O
A7 O
— Ground terminal
A8 O
A9 O
O
Address signal output to the S-RAM (IC751)
O
O
O
O
Address signal output terminal Not used (open)
O
O
O
Address signal output terminal Used for chip enable signal output to the S-RAM (IC751)
O
O
Address signal output terminal Not used (open)
I
x ao Wait signal input from the MPEG audio/video decoder (IC201)
y
I
Mode selection terminal (fixed at "H")
i
I Mode selection terminal (fixed at "L")
Φ
O
System clock signal output terminal Not used (open)
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