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Ë SAA7165WP (SUB VIDEO ASSY: IC4702)
VIDEO ENHANCEMENT D/A
» Pin Assignment
6
5
4
3
2
1
44
43
7
UV3
UV4
8
9
UV5
10
UV6
11
UV7
SAA7165
V
DDD1
12
V
13
SSD1
Y0
14
15
Y1
16
Y2
17
Y3
19
20 21
22 23
24 25 26 27 28
18
» Pin Function
Pin No.
Pin Name
1
REFL Y
2
CY
3
SUB
4
UV0
5
UV1
6
UV2
7
UV3
8
UV4
9
UV5
10
UV6
11
UV7
12
VDD D1
13
VSS D1
14
Y0
15
Y1
16
Y2
17
Y3
18
Y4
19
Y5
20
Y6
21
Y7
22
AP
23
SP
24
MC
25
LLC
26
HREF
27
RESET
» Block Diagram
42
41
40
Y7 to Y0
8
39
Y
38
V
SSA3
YUV-bus
UV7 to
37
V
DDA2
UN0
36
(B - Y)
8
35
V
SSA2
34
V
SSA1
33
(R - Y)
MC
24
LLC
25
32
V
DDA1
HREF
26
31
V
DDD2
RESET
27
30
V
SSD2
SCL
28
2
29
SDA
I
C-bus
SDA
29
I/O
Low reference of luminance DAC (connected to VSS A1)
I
Capacitor for luminance DAC (high reference)
I
Substrate (connected to VSS A1)
I
I
UV signal input bit UV7 (digital color-difference signal)
I
UV signal input bit UV6 (digital color-difference signal)
UV signal input bit UV5 (digital color-difference signal)
I
I
UV signal input bit UV4 (digital color-ifference signal)
UV signal input bit UV3 (digital color-difference signal)
I
UV signal input bit UV2 (digital color-difference signal)
I
I
UV signal input bit UV1 (digital color-difference signal)
UV signal input bit UV0 (digital color-difference signal)
I
+5V digital supply voltage 1
—
—
Digital ground 1 (0 V)
Y signal input bit Y7 (digital luminance signal)
I
I
Y signal input bit Y6 (digital luminance signal)
I
Y signal input bit Y5 (digital luminance signal)
Y signal input bit Y4 (digital luminance signal)
I
Y signal input bit Y3 (digital luminance signal)
I
Y signal input bit Y2 (digital luminance signal)
I
I
Y signal input bit Y1 (digital luminance signal)
Y signal input bit Y0 (digital luminance signal)
I
Connected to ground (action pin for testing)
—
—
Connected to ground (shift pin for testing)
Data cloack CREF (e.g.13.5MHz); at MC=HIGH, the LLC driver-by-two is inactive
I
I
Line-locked clock signal (LL27=27MHz)
I
Data clock for YUV data inputs (for active line 768Y or 640Y long)
Reset input (active LOW)
I
V
V
DDD1
DDD2
12
31
21 to 14
PEAKING
Y
AND
FORMATTER
CORING
data clock
11 to 4
UV
INTERPOLATION
FORMATTER
FILTER
TIMING
CONTROL
2
TEST
I
C-BUS
CONTROL
CONTROL
13
30
22
23
AP
V
V
SP
SSD1
SSD2
Function
71
64LHP5000
PROJECTOR UNIT
V
V
V
CUR V
DDA1
DDA2
DDA3
DDA4
32
37
40
41
42
25Ω
Y
DAC 3
DATA
25Ω
SWITCH
U
DAC 2
DCTI
V
DAC 1
25Ω
SAA7165
3
34
35
38
SUB
V
V
V
SSA1
SSA2
SSA3
2
C
Y
39
Y
1
REFL
Y
36
(B - Y)
44
REFL
UV
43
C
UV
33
(R - Y)
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