Sharp 64LHP5000 Service Manual page 58

64LHP5000
PROJECTOR UNIT
Ë PD5463B9 (TUNER µ-COM: IC2202)
SUB µ-COM
» Pin Function
Pin No. Pin Name
1 DH BLK
2 V BLK2
3 OPTION
4 VS
5 HS
6 NC
7 P.RST
8 (S)BUSY
9 (S)ENB
10 (S)DATA
11 V SIZE ADJ
12 H SIZE ADJ
13 H PHA ADJ
14 OSD ENB
15 (S)CLK
16 OSD DATA
17 OSD CLK
18 AVCC
19 HLF
20 RVCO
21 VHOLD
22 CC Y1
23 CNVSS
24 XIN
25 XOUT
26 VSS
27 VCC
28 OSC1
29 OSC2
30 RESET
31 V O/X1
32 V O/X2
33 CENT O/X
34 FRESH TONE
35 CNR SW
36 SDA4
37 SDA3
38 SCL4
39 SCL3
I/O
I CCD display sync signal double speed HBLK input
I CCD display sync signal VBLK input
I Voltage input for switching software destination
I Vertical sync input for detecting fH of component signal
I Horizontal sync input for detecting fH of component signal
– Unused
RESET output for RESET control of progressive BLOCK
O
(PE6001A9, PST9146N), TC9078F (aspect conversion IC)
O BUSY line for communication with main microprocessor
I ENB line for communication with main microprocessor
I/O DATA line for communication with main microprocessor
O PWM output for vertical size adjustment
O PWM output for horizontal size adjustment
O PWM output for horizontal position adjustment
O ENB output for PD0264A(OSD IC) control
I CLK line input for communication with main microprocessor
O DATA output for controlling PD0264 A (OSD IC)
O CLK output for controlling PD0264 A (OSD IC)
– Analog power supply. Connected to +5V.
– Connected to external part for CCD timing signal generation circuit
– Connected to external part for CCD timing signal generation circuit
– Connected to external part for CCD reference voltage generation circuit
I Input of video signal for main screen CCD and V CHIP detection
– Connected to VSS.
– Input pin of main clock generation circuit
– Output pin of main clock generation circuit
– Supplies to 0V
– Supplies +5V power supply
I Clock input for display
I/O Clock output for display
I RESET input
I Input for main signal input detection
I Input for sub signal input detection
I Input for center input detection
O Signal output for switching skin color compensation input range
O Control output for CNR ON/OFF
I2C BUS for CXA2069Q (AV selection SW), CXA1315M (DAC for
I/O
AV I/O) control
TC9078F (aspect conversion IC), 87C654 (line doubler control
O
microprocessor), SAA7165 (D/A conversion), I2C BUS for control
O Same as SDA4
O Same as SDA3
Function
58
ACT
Positive polarity
Positive polarity
P: L, S: H
Positive polarity
Positive polarity
–
RESET: H
H: BUSY
Communication permission: L
–
Size large: +, Size small: –
Size large: +, Size small: –
Move to right: –, Move to left: +
Communication permission: L
–
–
–
–
–
–
–
Positive polarity
–
–
–
–
–
–
–
Reset: L
Signal present: L
Signal present: L
Signal present: H
ON: L
ON: L
–
–
–
–