Sony DSR-300P Service Manual page 23

P96
HD/CBLK
N96
P139 P315
FH
N140 N315
P169
HBLK
N154
P66
HSYNC
N68
P22
P32
N22
N36
BF
P78
N76
EQ
P420
P34
N423
N32
P388
N387
VSYNC
P66
N68
H.R.
P90
N90
2FH P140 P169
N141 N169
( INNER CLOCK )
P145
N145
1/2H P454
VD
N455
FLD
FLD1
LALT
DSR-300/P(J,E)/V2
P908
N910
1H
P : PAL, SECAM
N : NTSC, PALM
CXD1267AN-T4 (SONY)FLAT PACKAGE
C-MOS VERTICAL CLOCK DRIVER FOR CCD
—TOP VIEW—
20
CPP1
CPP3 1 20 CPP1
19
CPP2
2 V 19 CPP2
H
3
DC IN
DC
3 18 DC
IN OUT 4
XSHT
6
XV1
XSHT 4 17 VSHT
7
XSG1
5
XV2
XV2 5 V 16
L
8
XV3
9
XSG2
XV1 6 GND 15 VO2
10
XV4
XSG1 7 14 VO1
XV3 8 13
XSG2 9 12 VO3
XV4 10 11 VO4
INPUT
DCIN : OPERATIONAL AMPLIFIRE
XSG1, XSG2 : SENSOR GATE PULSE
XSHT : SAMPLE AND HOLD PULSE
XV1 - XV4 : VERTICAL REGISTER TRANSMISSION CLOCK
OUTPUT
CPP3 : CHARGE PUMP
DC OUT : OPERATIONAL AMPLIFIRE
VSHT : SAMPLE AND HOLD PULSE
VO1 - VO4 : VERTICAL REGISTER TRANSMISSION CLOCK
INPUT OUTPUT
XV1, 3 XSG1, 2 XV2, 4 XSHT VO1, 3 VO2, 4
0 0 x x x
1 0 x x HI-Z x
x x x
0 1 GND
1 1 x x x
x x 0 x x GND
x x 1 x x
x x x 0 x x
x x x 1 x x
20
CPP1
CHARGE 1
CPP3
PUMP
19
CPP2
3
+
DC IN
18
DC OUT
_
17
4
VSHT
XSHT
6
XV1 14
VO1
7
XSG1
15
5
VO2
XV2
8
XV3 12
VO3
9
XSG2
10 11
XV4 VO4
1
CPP3
18
DC OUT
17
VSHT
14
VO1
15
VO2
12
VO3
11
VO4
VSHT
x
x
x
x
x
0 : LOW LEVEL
x
1 : HIGH LEVEL
x : DON'T CARE
HI-Z : HIGH IMPEDANCE
9-15
IC