Sn74Hc193Ans - Sony DSR-300P Service Manual

SN74HC193ANS (TI)FLAT PACKAGE
SN74HC193ANS-E05
C-MOS PRESETTABLE SYNCHRONOUS 4-BIT UP/DOWN COUNTER
—TOP VIEW—
B 1 V 16
( DATA B ) IN DD
QB 2 15
OUT
QA 3 14
OUT
CKDN ( DOWN CLOCK ) IN 4 13
CKUP 5 12
( UP CLOCK ) IN
QC 6 11
OUT
QD 7 10
OUT
8 9
GND
CONTROL INPUT
MODE
RD LD CKUP CKDN
x
1 x x RESET TO ZERO
0 0 x x PRESET
0 1 1 UP COUNT
0 1 1 DOWN COUNT
0 1 1 1 NO COUNT
CKUP
CO = • QA • QB • QC • QD
CKUP
COUNT = 15
( A = B = C = D = HIGH )
CO
CKDN QA QB QC QD
BRW = • • • •
CKDN
COUNT = 0
( A = B = C = D = LOW )
BRW
SN74HC32APW-E05 (TI)FLAT PACKAGE
TC74VHC32FS(EL) (TOSHIBA)FLAT PACKAGE
C-MOS QUAD 2-INPUT OR GATES
—TOP VIEW—
14 13 12 11 10 9 8
A
V
DD
B
GND
1 2 3 4 5 6 7
0 : LOW LEVEL
1 : HIGH LEVEL
SN74HCT541APW-E05 (TI)FLAT PACKAGE
TC74VHC541FS(EL) (TOSHIBA)FLAT PACKAGE
C-MOS BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS
—TOP VIEW—
G2
Y1 Y2 Y3 Y4 Y5 Y6 Y7
20 19 18 17 16 15 14 13 12
V
DD
1 2 3 4 5 6 7 8 9
G1
A1 A2 A3 A4 A5 A6 A7 A8
G1 G2 A Y
A Y
0 0 0 0
G1
0
G2 0 0 1 1
1
1 x x HI-Z
x
x 1 x HI-Z
HI-Z
DSR-300/P(J,E)/V2
11
LD
15 3
A QA
1 2
B QB
A
( DATA A ) IN
10
6
C QC
9 7
D QD
RD ( RESET ) IN
5 12
CKUP CO
BRW ( BORROW ) OUT
4 13
CKDN BRW
RD
CO
( CARRY ) OUT
14
LD ( LOAD ) IN
C ( DATA C ) IN
D ( DATA D ) IN
OUTPUT
COUNT
QD QC QB QA
0
0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7
0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15
1 1 1 1
0 : LOW LEVEL
1 : HIGH LEVEL
x : DON'T CARE
A
Y = Y
B
Y = A + B = A • B
A B Y
0 0 0
0 1 1
1 0 1
1 1 1
Y8
11
2 18
A1 Y1
3 17
A2 Y2
4 16
A3 Y3
5 15
A4 Y4
6 14
A5 Y5
13
7
Y6
A6
8 12
A7 Y7
GND
9 11
A8 Y8
10
G1 G2
1 19
: LOW LEVEL
: HIGH LEVEL
: DON'T CARE
: HIGH IMPEDANCE
SN74HC595ADB-E05 (TI)FLAT PACKAGE(SMALL)
C-MOS 8-BIT SERIAL-INPUT/SERIAL- OR PARALLEL-OUTPUT
SHIFT REGISTER WITH LATCHED 3-STATE OUTPUT
—TOP VIEW—
QB
1 V 16
OUT DD
QC 2 15 QA
OUT OUT
QD
OUT 3 14 SI
IN
QE
OUT 4 13 OE
IN
QF 5 12 LCK ( )
OUT IN
QG 11
OUT 6 SCK ( )
IN
QH
OUT 7 10 RESET
IN
8 GND 9 SQH
OUT
10
RESET
R R
D D
14
SI
D Q D Q
11
SCK
D Q
12
LCK
13
OE
15
QA
SN74HC74APW-E05 (TI)FLAT PACKAGE
TC74VHC74FS(EL) (TOSHIBA)FLAT PACKAGE
C-MOS DUAL D-TYPE FLIP-FLOPS WITH DIRECT SET/RESET
—TOP VIEW—
14 13 12 11 10 9 8
V
DD
Q Q
S R
D D
D
Q
Q
S
D R
D
D
GND
1 2 3 4 5 6 7
4
10
S
2 D 5 12 S 9
D
D Q D Q
3 11
6 8
Q Q
R R
D
D
1
13
14 15
SI QA
1
QB
2
10
RESET QC
3
QD
4
QE
5
QF
6
QG
7
QH
11
SCK
12
LCK
9
SQH
OE
13
OE : OUTPUT ENABLE INPUT
LCK : LATCH CLOCK INPUT
SCK : SHIFT CLOCK INPUT
RESET : SHIFT-REGISTER RESET INPUT
SI : SERIAL N
QA - QH : PARALLEL OUTPUT
SQH : SERIAL OUT
R
D
9
D Q SQH
D Q
7
QH
INPUTS OUTPUTS
S R CK D Qn+1 Qn+1
D D
0 1 x x 1 0
1 0 x x 0 1
0 0 x x 1 1
1 1 1 0
1
1 0 0 1
1
x Qn
1 1 0 Qn
0 : LOW LEVEL
1 : HIGH LEVEL
x : DON'T CARE
9-43
IC